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2022.02
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@vfalanis vfalanis released this 07 Mar 15:07
· 138 commits to master since this release
2022.02
53cb18e

Icicle Kit Reference Design 2022.02

This release moves all DDR in the icicle kit reference design to 64 bit addresses only & is incompatible with previous releases.

Libero version

This release is intended for use with Libero 2021.3.

Pre-built programming files

The Icicle-Kit-2022.02.zip release asset file contains a FlashPro Express programming file including both this Libero FPGA design and Hart Software Services 0.99.29. This programming file can be used to program an Icicle Kit's FPGA and eNVM without having to run through the Libero FPGA flow or building the HSS.

Changes since last release

  • Added support for Libero 2021.3.
  • Added AXI address shim core to offset addresses from the PCIe block
  • Removed unused PCIe LSRAM
  • Added core I2C and core UART to the fabric
  • Updated core versions in the design
  • Disabled MSS QSPI and enabled SPI1 instead
  • Added a Linux and bare metal design generation target - this is due to memory map changes in Linux, the only difference in these profiles is the MSS DDR configuration.
Assets 3
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