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v2022.09
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@ConchuOD ConchuOD released this 30 Sep 12:52
· 45 commits to master since this release
v2022.09
371998d

Icicle Kit Reference Design Release v2022.09

Changes since last release

  • Locked CCC used to generate fabric clocks to the NW PLL so the clock frequency can be read by embedded software at run time
    • Updated the FIC 3 clock frequency from 62.5MHz to 50MHz
  • Memory map updates
    • Updated the base addresses of FIC 0 peripherals
    • Moved the PCIe to solely operate on in the FIC 1 domain
    • Updated the base address of FIC 3 peripherals
    • The memory map table in the readme should be consulted for the updated base addresses of all peripherals
  • Wrapped components in SmartDesigns
    • FIC 0 components are now contained in a "FIC_0_PERIPHERALS" SmartDesign
    • FIC 1 components are now contained in a "FIC_1_PERIPHERALS" SmartDesign
    • FIC 3 components are now contained in a "FIC_3_PERIPHERALS" SmartDesign
    • FIC 3 address generation is contained in a "FIC_3_ADDRESS_GENERATION" SmartDesign
    • Wrapped the MSS component in a SmartDesign to contain bibufs and additional components used to interface the MSS with the fabric
    • Wrapped CoreI2C components in a SmartDesign to contain bibufs
  • Updated all argument designs to support the latest base configuration
    • Removed the AXI_ADDRESS_SHIM in the "BAREMETAL" argument configuration as this is expected to be a 32 bit configuration
  • Added an additional CoreI2C to interface with the "ID_SC" and "ID_SD" pins of the RPi interface to read DT overlays from eeproms on RPi hats
  • Renamed the "SDIO_register" to "fabric_sd_emmc_demux_select" to match the naming convention for embedded software
  • Updated the HSS_UPDATE feature to use the new hex file naming convention in the HSS
  • Updated the Tcl infrastructure to use wild cards for SgCores in the design - this should allow independence from Libero versions
  • Removed the initial Libero version check in the base Tcl scripts
  • Updated readme and block diagrams with the latest memory map configurations
  • The "VECTORBLOX" argument design is now featured in the readme as a build target to add the VectorBlox CNN to the FPGA fabric

Tested Libero version

This release has been tested with Libero SoC v2022.2

Pre-built programming files

The MPFS_ICICLE_BASE_DESIGN_2022_09.zip release asset contains a FlashPro Express programming file including both this Libero FPGA design and Hart Software Services release v2022.09.
This programming file can be used to program an Icicle Kit's FPGA and eNVM without having to run through the Libero FPGA flow or building the HSS.

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