Skip to content

v2023.02
Compare
Choose a tag to compare
@vfalanis vfalanis released this 28 Feb 12:33
· 5 commits to master since this release
v2023.02
This tag was signed with the committer’s verified signature.
vfalanis Valentina Alanis
GPG key ID: C3B9E9144BB2A387
Learn about vigilant mode.
2dc7cc2

Icicle Kit Reference Design Release v2023.02

Changes since last release

  • Re-generate the MSS configuration file with the 2022.3 MSS configurator
  • Update MSS Configuration to overlay DDR memory locations
    • The 32 bit cached, 32 bit non-cached, 38 bit cached and 38 bit non-cached DDR now point to the same physical addresses (0x0) of DDR in the Linux configuration
  • Add a try error block around downloaded cores - if a core can't be downloaded, e.g. on a system with no internet access, the script will continue to run and only fail if a core isn't present in a vault.
  • Use latest version of CCC SG core in Vectorblox and DRI_CCC_DEMO argument designs
  • Add support for SMARTHLS argument design which allows the design and generation of a hardware module described in C++ using Microchip's SmartHLS tool
    • IMPORTANT: This flag is part of an Early Access Program for SmartHLS. If you are interested, please contact your local FAE or email us at SmartHLS@microchip.com for more details on how to enable this feature.

Tested Libero Version

This release has been tested with Libero SoC v2022.3

Pre-built programming files

The MPFS_ICICLE_BASE_DESIGN_2023_02.zip release asset contains a FlashPro Express programming file including both this Libero FPGA design and Hart Software Services release v2023.02.
This programming file can be used to program an Icicle Kit's FPGA and eNVM without having to run through the Libero FPGA flow or building the HSS.

Assets 8
Loading