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axi_xbar_unmuxed: add to Readme, fusesoc, src_files
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micprog committed Jul 19, 2024
1 parent f745db2 commit 587a7c0
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1 change: 1 addition & 0 deletions README.md
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Expand Up @@ -67,6 +67,7 @@ In addition to the documents linked in the following table, we are setting up [d
| [`axi_to_axi_lite`](src/axi_to_axi_lite.sv) | AXI4 to AXI4-Lite protocol converter. | |
| [`axi_to_mem`](src/axi_to_mem.sv) | AXI4 to memory protocol (req, gnt, rvalid) converter. Additional banked, interleaved, split variant. | |
| [`axi_xbar`](src/axi_xbar.sv) | Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports. | [Doc](doc/axi_xbar.md) |
| [`axi_xbar_unmuxed`](src/axi_xbar_unmuxed.sv) | Demux side of fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports. | [Doc](doc/axi_xbar.md) |
| [`axi_xp`](src/axi_xp.sv) | AXI Crosspoint (XP) with homomorphous slave and master ports. | |
| [`axi_zero_mem`](src/axi_zero_mem.sv) | AXI-attached /dev/zero. All reads will be zero, writes are absorbed. | |

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4 changes: 3 additions & 1 deletion axi.core
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Expand Up @@ -64,7 +64,7 @@ filesets:
- src/axi_interleaved_xbar.sv
- src/axi_iw_converter.sv
- src/axi_lite_xbar.sv
- src/axi_xbar.sv
- src/axi_xbar_unmuxed.sv
- src/axi_to_mem_banked.sv
- src/axi_to_mem_interleaved.sv
- src/axi_to_mem_split.sv
Expand All @@ -73,6 +73,8 @@ filesets:
- src/axi_sim_mem.sv
- src/axi_test.sv
# Level 5
- src/axi_xbar.sv
# Level 6
- src/axi_xp.sv
file_type : systemVerilogSource
depend :
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4 changes: 3 additions & 1 deletion src_files.yml
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Expand Up @@ -63,11 +63,13 @@ axi:
- src/axi_interleaved_xbar.sv
- src/axi_iw_converter.sv
- src/axi_lite_xbar.sv
- src/axi_xbar.sv
- src/axi_xbar_unmuxed.sv
- src/axi_to_mem_banked.sv
- src/axi_to_mem_interleaved.sv
- src/axi_to_mem_split.sv
# Level 5
- src/axi_xbar.sv
# Level 6
- src/axi_xp.sv

axi_sim:
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