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Properly handle response code in axi_to_detailed_mem #320
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.github/workflows/gitlab-ci.yml
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As a not. Lets not forget the changelog to be updated accordingly.
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Added info in the changelog
Bender.yml
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@@ -19,7 +19,7 @@ package: | |||
- "Florian Zaruba <zarubaf@iis.ee.ethz.ch>" | |||
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dependencies: | |||
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.27.0 } | |||
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", rev: "be16fe6efa97af39ca258e398f37b7910e636e02" } |
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Improved version of mem_to_banks.
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Updated common_cells
to a proper version tag with the required changes
src/axi_to_detailed_mem.sv
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logic resp_b_err, resp_b_exokay, resp_r_err, resp_r_exokay; | ||
for (genvar i = 0; i < NumBanks; i++) begin | ||
assign meta_buf_bank_strb[i] = meta_buf.strb[i*NumBytesPerBank +: NumBytesPerBank]; | ||
assign meta_buf_size_enable[i] = i*NumBytesPerBank + NumBytesPerBank > (meta_buf.addr % DataWidth/8) && |
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Quite a full line. Can you maybe explain a bit in more details what is going on here?
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I agree, maybe at least one further level of parentheses would also help with understanding this rather complex condition.
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I expanded the explanation to clarify what is going on and added an additional level of parentheses for clearer grouping.
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Can you comment a bit more what is going on exactly in the pretty dense code blocks added?
src/axi_to_detailed_mem.sv
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logic resp_b_err, resp_b_exokay, resp_r_err, resp_r_exokay; | ||
for (genvar i = 0; i < NumBanks; i++) begin | ||
assign meta_buf_bank_strb[i] = meta_buf.strb[i*NumBytesPerBank +: NumBytesPerBank]; | ||
assign meta_buf_size_enable[i] = i*NumBytesPerBank + NumBytesPerBank > (meta_buf.addr % DataWidth/8) && |
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I agree, maybe at least one further level of parentheses would also help with understanding this rather complex condition.
src/axi_to_detailed_mem.sv
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logic [NumBanks-1:0] meta_buf_bank_strb, meta_buf_size_enable; | ||
logic resp_b_err, resp_b_exokay, resp_r_err, resp_r_exokay; | ||
for (genvar i = 0; i < NumBanks; i++) begin | ||
assign meta_buf_bank_strb[i] = meta_buf.strb[i*NumBytesPerBank +: NumBytesPerBank]; |
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meta_buf.strb
is of type axi_strb_t
but meta_buf_bank_strb
is a 1-bit logic
(for every bank).
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I also discovered this and appropriately fixed the issue, ensuring correct mapping:
assign meta_buf_bank_strb[i] = |meta_buf.strb[i*NumBytesPerBank +: NumBytesPerBank];
Fixes #319
Requires pulp-platform/common_cells#194 to be released