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micprog committed Aug 5, 2024
1 parent 559bcbd commit 517ffad
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Showing 5 changed files with 104 additions and 43 deletions.
44 changes: 22 additions & 22 deletions .github/workflows/ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -21,13 +21,13 @@ jobs:
check-clean:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v3
- uses: actions/setup-python@v4
- uses: actions/checkout@v4
- uses: actions/setup-python@v5
with:
python-version: '3.9'
cache: 'pip'
- name: Setup Graphviz
uses: ts-graphviz/setup-graphviz@v1
uses: ts-graphviz/setup-graphviz@v2
- name: Install Bender
run: make bender
- name: Install Morty
Expand All @@ -42,13 +42,13 @@ jobs:
check-stale:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v3
- uses: actions/setup-python@v4
- uses: actions/checkout@v4
- uses: actions/setup-python@v5
with:
python-version: '3.9'
cache: 'pip'
- name: Setup Graphviz
uses: ts-graphviz/setup-graphviz@v1
uses: ts-graphviz/setup-graphviz@v2
- name: Install Bender
run: make bender
- name: Install Morty
Expand All @@ -67,8 +67,8 @@ jobs:
matrix:
lint_check: [license, python]
steps:
- uses: actions/checkout@v3
- uses: actions/setup-python@v4
- uses: actions/checkout@v4
- uses: actions/setup-python@v5
with:
python-version: '3.9'
cache: 'pip'
Expand All @@ -86,13 +86,13 @@ jobs:
runs-on: ubuntu-latest
needs: [check-clean, check-stale]
steps:
- uses: actions/checkout@v3
- uses: actions/checkout@v4
if: ${{ github.event_name == 'push' }}
- uses: actions/checkout@v3
- uses: actions/checkout@v4
if: ${{ github.event_name == 'pull_request' }}
with:
ref: ${{ github.event.pull_request.head.sha }}
- uses: actions/setup-python@v4
- uses: actions/setup-python@v5
with:
python-version: '3.9'
cache: 'pip'
Expand Down Expand Up @@ -120,11 +120,11 @@ jobs:
runs-on: ubuntu-latest
needs: lint
steps:
- uses: actions/checkout@v3
- uses: actions/checkout@v4
- name: List contributors
run: scripts/list-contributors | tee contributions.txt
- name: Upload contributions.txt
uses: actions/upload-artifact@v2
uses: actions/upload-artifact@v4
with:
name: contributions
path: contributions.txt
Expand All @@ -134,11 +134,11 @@ jobs:
needs: lint
continue-on-error: true
steps:
- uses: actions/checkout@v3
- uses: actions/checkout@v4
- name: List todos
run: scripts/list-todos | tee open_todos.txt
- name: Upload todos.txt
uses: actions/upload-artifact@v2
uses: actions/upload-artifact@v4
with:
name: open_todos
path: open_todos.txt
Expand All @@ -150,12 +150,12 @@ jobs:
env:
MORTY: ./morty
steps:
- uses: actions/checkout@v3
- uses: actions/checkout@v4
- name: Install Bender
run: make bender
- name: Setup Graphviz
uses: ts-graphviz/setup-graphviz@v1
- uses: actions/setup-python@v4
uses: ts-graphviz/setup-graphviz@v2
- uses: actions/setup-python@v5
with:
python-version: '3.9'
cache: 'pip'
Expand All @@ -170,19 +170,19 @@ jobs:
- name: Graph
run: make graph
- name: Upload doc
uses: actions/upload-artifact@v2
uses: actions/upload-artifact@v4
with:
name: doc
path: doc/morty
retention-days: 7
- name: Upload graph
uses: actions/upload-artifact@v2
uses: actions/upload-artifact@v4
with:
name: graph
path: doc/morty-graph
retention-days: 7
- name: Upload pickle
uses: actions/upload-artifact@v2
uses: actions/upload-artifact@v4
with:
name: pickle
path: pickle
Expand All @@ -206,4 +206,4 @@ jobs:
steps:
- name: Deploy to Github Pages
id: deployment
uses: actions/deploy-pages@v1
uses: actions/deploy-pages@v4
25 changes: 17 additions & 8 deletions Bender.lock
Original file line number Diff line number Diff line change
@@ -1,16 +1,23 @@
packages:
apb:
revision: 77ddf073f194d44b9119949d2421be59789e69ae
version: 0.2.4
source:
Git: https://github.com/pulp-platform/apb.git
dependencies:
- common_cells
axi:
revision: af8b0ce2653997301b1b792c4c6d207b95f63a56
version: 0.39.0-beta.2
revision: 587355b77b8ce94dcd600efbd5d5bd118ff913a7
version: 0.39.4
source:
Git: https://github.com/pulp-platform/axi.git
dependencies:
- common_cells
- common_verification
- tech_cells_generic
common_cells:
revision: b59eca3c1747b28022573e37aa91a151808d1db5
version: 1.26.0
revision: c27bce39ebb2e6bae52f60960814a2afca7bd4cb
version: 1.37.0
source:
Git: https://github.com/pulp-platform/common_cells.git
dependencies:
Expand All @@ -23,16 +30,18 @@ packages:
Git: https://github.com/pulp-platform/common_verification.git
dependencies: []
register_interface:
revision: 9fc63015615acb11111e4bc3e858381e3e72405d
version: 0.3.6
revision: ae616e5a1ec2b41e72d200e5ab09c65e94aebd3d
version: 0.4.4
source:
Git: https://github.com/pulp-platform/register_interface.git
dependencies:
- apb
- axi
- common_cells
- common_verification
tech_cells_generic:
revision: e6226a6f374eb88fed84d4989bb3f066cb470f33
version: 0.2.9
revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf
version: 0.2.13
source:
Git: https://github.com/pulp-platform/tech_cells_generic.git
dependencies:
Expand Down
4 changes: 2 additions & 2 deletions Bender.yml
Original file line number Diff line number Diff line change
Expand Up @@ -9,10 +9,10 @@ package:
- "Wolfgang Roenninger <wroennin@ethz.ch>"

dependencies:
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.0-beta.2 }
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.4 }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 }
common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 }
register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.6 }
register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 }
tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.9 }

export_include_dirs:
Expand Down
8 changes: 4 additions & 4 deletions src/axi_llc_hit_miss.sv
Original file line number Diff line number Diff line change
Expand Up @@ -14,17 +14,17 @@
/// During initialisation no descriptors can enter the unit.
///
/// This unit keeps track of which cache lines are currently in use by descriptors
/// downstream with the help od a bloom filter. If there is a new descriptor, which
/// will access a cache line currently in use, it wil be stalled untill the line is
/// downstream with the help of a bloom filter. If there is a new descriptor, which
/// will access a cache line currently in use, it will be stalled until the line is
/// unlocked. This is to prevent data corruption.
///
/// There is an array of counter which keep track which IDs of descriptors
/// There is an array of counters which keep track which IDs of descriptors
/// are currently in the miss pipeline. All subsequent hits which normally would go
/// through the bypass will get sent also towards the miss pipeline. However their
/// eviction and refill fields will not be set. This is to clear the unit from
/// descriptors, so that new ones from other IDs can use the hit bypass.
module axi_llc_hit_miss #(
/// Stattic LLC configuration struct.
/// Static LLC configuration struct.
parameter axi_llc_pkg::llc_cfg_t Cfg = axi_llc_pkg::llc_cfg_t'{default: '0},
/// AXI parameter configuration
parameter axi_llc_pkg::llc_axi_cfg_t AxiCfg = axi_llc_pkg::llc_axi_cfg_t'{default: '0},
Expand Down
66 changes: 59 additions & 7 deletions src/axi_llc_reg_top.sv
Original file line number Diff line number Diff line change
Expand Up @@ -8,12 +8,12 @@
`include "common_cells/assertions.svh"

module axi_llc_reg_top #(
parameter type reg_req_t = logic,
parameter type reg_rsp_t = logic,
parameter int AW = 7
parameter type reg_req_t = logic,
parameter type reg_rsp_t = logic,
parameter int AW = 7
) (
input clk_i,
input rst_ni,
input logic clk_i,
input logic rst_ni,
input reg_req_t reg_req_i,
output reg_rsp_t reg_rsp_o,
// To HW
Expand All @@ -33,7 +33,7 @@ module axi_llc_reg_top #(
// register signals
logic reg_we;
logic reg_re;
logic [AW-1:0] reg_addr;
logic [BlockAw-1:0] reg_addr;
logic [DW-1:0] reg_wdata;
logic [DBW-1:0] reg_be;
logic [DW-1:0] reg_rdata;
Expand All @@ -54,7 +54,7 @@ module axi_llc_reg_top #(

assign reg_we = reg_intf_req.valid & reg_intf_req.write;
assign reg_re = reg_intf_req.valid & ~reg_intf_req.write;
assign reg_addr = reg_intf_req.addr;
assign reg_addr = reg_intf_req.addr[BlockAw-1:0];
assign reg_wdata = reg_intf_req.wdata;
assign reg_be = reg_intf_req.wstrb;
assign reg_intf_rsp.rdata = reg_rdata;
Expand Down Expand Up @@ -731,3 +731,55 @@ module axi_llc_reg_top #(
`ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))

endmodule

module axi_llc_reg_top_intf
#(
parameter int AW = 7,
localparam int DW = 32
) (
input logic clk_i,
input logic rst_ni,
REG_BUS.in regbus_slave,
// To HW
output axi_llc_reg_pkg::axi_llc_reg2hw_t reg2hw, // Write
input axi_llc_reg_pkg::axi_llc_hw2reg_t hw2reg, // Read
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
localparam int unsigned STRB_WIDTH = DW/8;

`include "register_interface/typedef.svh"
`include "register_interface/assign.svh"

// Define structs for reg_bus
typedef logic [AW-1:0] addr_t;
typedef logic [DW-1:0] data_t;
typedef logic [STRB_WIDTH-1:0] strb_t;
`REG_BUS_TYPEDEF_ALL(reg_bus, addr_t, data_t, strb_t)

reg_bus_req_t s_reg_req;
reg_bus_rsp_t s_reg_rsp;

// Assign SV interface to structs
`REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave)
`REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp)



axi_llc_reg_top #(
.reg_req_t(reg_bus_req_t),
.reg_rsp_t(reg_bus_rsp_t),
.AW(AW)
) i_regs (
.clk_i,
.rst_ni,
.reg_req_i(s_reg_req),
.reg_rsp_o(s_reg_rsp),
.reg2hw, // Write
.hw2reg, // Read
.devmode_i
);

endmodule


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