Merge pull request #12 from pulp-platform/fix_ecc_wrap

Fix ECC SRAM wrap
pulp-platform · Apr 12, 2023 · 464f264 · 464f264
2 parents 4c029cb + d44b90c
commit 464f264
Show file tree

Hide file tree

Showing 6 changed files with 40 additions and 20 deletions.
diff --git a/rtl/ODRG_unit/odrg_manager_reg_top.sv b/rtl/ODRG_unit/odrg_manager_reg_top.sv
@@ -33,7 +33,7 @@ module odrg_manager_reg_top #(
   // register signals
   logic           reg_we;
   logic           reg_re;
-  logic [AW-1:0]  reg_addr;
+  logic [BlockAw-1:0]  reg_addr;
   logic [DW-1:0]  reg_wdata;
   logic [DBW-1:0] reg_be;
   logic [DW-1:0]  reg_rdata;
@@ -54,7 +54,7 @@ module odrg_manager_reg_top #(
 
   assign reg_we = reg_intf_req.valid & reg_intf_req.write;
   assign reg_re = reg_intf_req.valid & ~reg_intf_req.write;
-  assign reg_addr = reg_intf_req.addr;
+  assign reg_addr = reg_intf_req.addr[BlockAw-1:0];
   assign reg_wdata = reg_intf_req.wdata;
   assign reg_be = reg_intf_req.wstrb;
   assign reg_intf_rsp.rdata = reg_rdata;

diff --git a/rtl/ecc_wrap/ecc_manager_reg_top.sv b/rtl/ecc_wrap/ecc_manager_reg_top.sv
@@ -33,7 +33,7 @@ module ecc_manager_reg_top #(
   // register signals
   logic           reg_we;
   logic           reg_re;
-  logic [AW-1:0]  reg_addr;
+  logic [BlockAw-1:0]  reg_addr;
   logic [DW-1:0]  reg_wdata;
   logic [DBW-1:0] reg_be;
   logic [DW-1:0]  reg_rdata;
@@ -54,7 +54,7 @@ module ecc_manager_reg_top #(
 
   assign reg_we = reg_intf_req.valid & reg_intf_req.write;
   assign reg_re = reg_intf_req.valid & ~reg_intf_req.write;
-  assign reg_addr = reg_intf_req.addr;
+  assign reg_addr = reg_intf_req.addr[BlockAw-1:0];
   assign reg_wdata = reg_intf_req.wdata;
   assign reg_be = reg_intf_req.wstrb;
   assign reg_intf_rsp.rdata = reg_rdata;

diff --git a/rtl/ecc_wrap/ecc_sram_wrap.sv b/rtl/ecc_wrap/ecc_sram_wrap.sv
@@ -282,6 +282,13 @@ module ecc_sram_wrap #(
     end
   end
 
+  logic [(EnableTestMask ? ProtectedWidth : 1)-1:0] sram_be;
+  if (EnableTestMask) begin : gen_be
+    assign sram_be = ~test_write_mask_ni;
+  end else begin : gen_be_const
+    assign sram_be = 1'b1;
+  end
+
   tc_sram #(
     .NumWords  ( BankSize                            ), // Number of Words in data array
     .DataWidth ( ProtectedWidth                      ), // Data signal width
@@ -295,17 +302,16 @@ module ecc_sram_wrap #(
     .clk_i,                                                   // Clock
     .rst_ni,                                                  // Asynchronous reset active low
 
-    .req_i   ( bank_final_req                              ), // request
-    .we_i    ( bank_final_we                               ), // write enable
-    .addr_i  ( bank_final_add                              ), // request address
-    .wdata_i ( bank_scrub_wdata                            ), // write data
-    .be_i    ( EnableTestMask ? ~test_write_mask_ni : 1'b1 ), // write byte enable
+    .req_i   ( bank_final_req    ), // request
+    .we_i    ( bank_final_we     ), // write enable
+    .addr_i  ( bank_final_add    ), // request address
+    .wdata_i ( bank_scrub_wdata  ), // write data
+    .be_i    ( sram_be           ), // write byte enable
 
-    .rdata_o (  bank_scrub_rdata                            )  // read data
+    .rdata_o (  bank_scrub_rdata )  // read data
   );
 
-  // These registers are to avoid writes during scan testing.
-  // Please ensure these registers are not scanned
+  // These registers are to avoid writes during scan testing. Please ensure these registers are not scanned
   always_ff @(posedge clk_i) begin : proc_test_req_ff
     test_req_q <= test_req_d;
     test_add_q <= test_add_d;

diff --git a/rtl/pulpissimo_tcls/tcls_manager_reg_top.sv b/rtl/pulpissimo_tcls/tcls_manager_reg_top.sv
@@ -33,7 +33,7 @@ module tcls_manager_reg_top #(
   // register signals
   logic           reg_we;
   logic           reg_re;
-  logic [AW-1:0]  reg_addr;
+  logic [BlockAw-1:0]  reg_addr;
   logic [DW-1:0]  reg_wdata;
   logic [DBW-1:0] reg_be;
   logic [DW-1:0]  reg_rdata;
@@ -54,7 +54,7 @@ module tcls_manager_reg_top #(
 
   assign reg_we = reg_intf_req.valid & reg_intf_req.write;
   assign reg_re = reg_intf_req.valid & ~reg_intf_req.write;
-  assign reg_addr = reg_intf_req.addr;
+  assign reg_addr = reg_intf_req.addr[BlockAw-1:0];
   assign reg_wdata = reg_intf_req.wdata;
   assign reg_be = reg_intf_req.wstrb;
   assign reg_intf_rsp.rdata = reg_rdata;

diff --git a/run_tests.sh b/run_tests.sh
@@ -20,15 +20,15 @@ VSIM_LOGFILE=vsim.log
 
 bender script vsim -t test -t rtl > compile.tcl
 
-"$VSIM" -c -do 'source compile.tcl; quit' > vcom.log
+$VSIM -c -do 'source compile.tcl; quit' > vcom.log
 
 rm -f $VSIM_LOGFILE
 
 call_vsim() {
   if [ $1 == tb_ecc_sram ]; then
-    echo "source test/ecc_sram_fault_injection.tcl; run -all" | "$VSIM" "$@" >> $VSIM_LOGFILE 2>&1
+    echo "source test/ecc_sram_fault_injection.tcl; run -all" | $VSIM "$@" >> $VSIM_LOGFILE 2>&1
   else
-    echo "run -all" | "$VSIM" "$@" >> $VSIM_LOGFILE 2>&1
+    echo "run -all" | $VSIM "$@" >> $VSIM_LOGFILE 2>&1
   fi
   echo "  --> $@"
   tail -3 $VSIM_LOGFILE
@@ -40,7 +40,8 @@ call_vsim tb_tmr_voter
 call_vsim tb_tmr_voter_detect
 call_vsim tb_tmr_word_voter
 call_vsim tb_bitwise_tmr_voter
-call_vsim tb_ecc_sram -voptargs="+acc=nr"
+call_vsim tb_ecc_sram -voptargs="+acc=nr" -GEnableTestMask=0
+call_vsim tb_ecc_sram -voptargs="+acc=nr" -GEnableTestMask=1
 call_vsim -GDataWidth=8 tb_ecc_secded
 call_vsim -GDataWidth=16 tb_ecc_secded
 call_vsim -GDataWidth=32 tb_ecc_secded

diff --git a/test/tb_ecc_sram.sv b/test/tb_ecc_sram.sv
@@ -12,7 +12,8 @@
 // based on tb_tc_sram.sv in tech_cells_generic
 
 module tb_ecc_sram #(
-  parameter int unsigned InputECC = 0
+  parameter int unsigned InputECC = 0,
+  parameter int unsigned EnableTestMask = 0
 );
 
   localparam BankSize       = 256;
@@ -148,18 +149,30 @@ module tb_ecc_sram #(
   ecc_sram_wrap #(
     .BankSize         ( BankSize       ),
     .InputECC         ( 0              ),
+    .EnableTestMask   ( EnableTestMask ),
     .UnprotectedWidth ( DataWidth      ),
     .ProtectedWidth   ( ProtectedWidth )
   ) i_dut (
     .clk_i        ( clk ),
     .rst_ni       ( rst_n ),
+    .test_enable_i        ('0),
+
+    .scrub_trigger_i      ('0),
+    .scrubber_fix_o       (),
+    .scrub_uncorrectable_o(),
+
     .tcdm_wdata_i ( wdata ),
     .tcdm_add_i   ( addr  ),
     .tcdm_req_i   ( req   ),
     .tcdm_wen_i   ( wen   ),
     .tcdm_be_i    ( be    ),
     .tcdm_rdata_o ( rdata ),
-    .tcdm_gnt_o   ( gnt   )
+    .tcdm_gnt_o   ( gnt   ),
+
+    .single_error_o       (),
+    .multi_error_o        (),
+
+    .test_write_mask_ni ('0)
   );
 
   /***********************