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update for lgtm notices
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ttt-t3r committed Nov 6, 2022
1 parent a69beeb commit 0cad408
Showing 1 changed file with 33 additions and 30 deletions.
63 changes: 33 additions & 30 deletions pyocd/target/builtin/target_ATSAML11xxxx.py
Original file line number Diff line number Diff line change
Expand Up @@ -17,16 +17,14 @@
import logging
from time import sleep

from typing import (Callable, Dict, List, Optional, overload, Sequence, Union, TYPE_CHECKING)
from typing import (overload, TYPE_CHECKING)
from ...core import exceptions
from ...core.target import Target
from ...coresight.coresight_target import CoreSightTarget
from ...coresight.cortex_m import CortexM
from ...coresight import dap
from ...core.memory_map import (FlashRegion, RamRegion, MemoryMap, MemoryType)
from ...core.memory_map import (FlashRegion, RamRegion, MemoryMap)
from ...debug.svd.loader import SVDFile
from ...utility.timeout import Timeout
from ...probe.debug_probe import DebugProbe

SCS_DHCSR = 0xE000EDF0
SCS_DHCSR_S_SDE = 0x00100000
Expand Down Expand Up @@ -160,7 +158,7 @@ def _bootrom_data(self, data):
# Timed out
LOG.error("timeout")
return False
return True
return True

def _bootrom_cmd(self, cmd):
self.write32(DSU_BCC0, BOOTROM_CMD_PREFIX | cmd)
Expand All @@ -174,7 +172,7 @@ def _bootrom_cmd(self, cmd):
# Timed out
LOG.error("timeout")
return False
return True
return True

def _bootrom_status(self, expected = None):
with Timeout(MASS_ERASE_TIMEOUT) as to:
Expand All @@ -184,17 +182,14 @@ def _bootrom_status(self, expected = None):
break
sleep(0.1)
else:
LOG.error("timeout")
return None
status = self.read32(DSU_BCC1)
if status & 0xffffff00 != BOOTROM_SIG_PREFIX:
LOG.error("signal prefix %x", status)
return None
res = status & 0xff
if (expected != None) and (res != expected):
LOG.error("unexpected response %x %x", res, expected)
return None
return res
raise exceptions.TimeoutError("timeout waiting for status")
status = self.read32(DSU_BCC1)
if status & 0xffffff00 != BOOTROM_SIG_PREFIX:
raise exceptions.InternalError("unexpected prefix 0x%x", status)
res = status & 0xff
if (expected != None) and (res != expected):
return exceptions.InternalError("unexpected response %x %x", res, expected)
return status

def _cold_plug(self):
self.session.probe.assert_reset_with_clk_low(True)
Expand All @@ -207,9 +202,9 @@ def _cold_plug(self):
self.dp.connect()
self.flush()
break
sleep(0.1)
except exceptions.TransferError:
self.flush()
sleep(0.1)

# read CRSTEXT
with Timeout(5.0) as t_o:
Expand Down Expand Up @@ -267,27 +262,26 @@ def mass_erase(self):
status = self._bootrom_cmd(BOOTROM_CMD_INIT)
if status == False:
raise exceptions.TimeoutError("bootrom command write timeout")

status = self._bootrom_status(BOOTROM_STATUS_SIG_COMM)
self._bootrom_status(BOOTROM_STATUS_SIG_COMM)

status = self._bootrom_cmd(BOOTROM_CMD_CE2)
if status == False:
raise exceptions.TimeoutError("bootrom command write timeout")
status = self._bootrom_status(BOOTROM_STATUS_SIG_CMD_VALID)
self._bootrom_status(BOOTROM_STATUS_SIG_CMD_VALID)

status = self._bootrom_data(cekey0)
if status == None:
if status == False:
raise exceptions.TimeoutError("bootrom data 0 write timeout")
status = self._bootrom_data(cekey1)
if status == None:
if status == False:
raise exceptions.TimeoutError("bootrom data 1 write timeout")
status = self._bootrom_data(cekey2)
if status == None:
if status == False:
raise exceptions.TimeoutError("bootrom data 2 write timeout")
status = self._bootrom_data(cekey3)
if status == None:
if status == False:
raise exceptions.TimeoutError("bootrom data 3 write timeout")
status = self._bootrom_status(BOOTROM_STATUS_SIG_CMD_SUCCESS)
self._bootrom_status(BOOTROM_STATUS_SIG_CMD_SUCCESS)

self.reset(Target.ResetType.HW)

Expand Down Expand Up @@ -327,13 +321,20 @@ def reset_and_halt(self, reset_type=None):
self.halt()
return

borrowed_bp = None
have_bp_set = self.find_breakpoint(reset_vec)
if have_bp_set == None:
if have_bp_set is None:
if self.set_breakpoint(reset_vec):
self.bp_manager.flush()
TRACE.info("Set breakpoint at 0x%08x", reset_vec)
TRACE.debug("Set breakpoint at 0x%08x", reset_vec)
else:
LOG.info("Failed to set breakpoint at 0x%08x", reset_vec)
borrowed_bp = self.bp_manager.get_breakpoints()[0]
self.remove_breakpoint(borrowed_bp)
self.bp_manager.flush()
if self.set_breakpoint(reset_vec):
self.bp_manager.flush()
else:
LOG.info("Failed to set breakpoint at 0x%08x", reset_vec)

self.reset(reset_type)

Expand All @@ -346,9 +347,11 @@ def reset_and_halt(self, reset_type=None):
else:
LOG.warning("Timed out waiting for core to halt after reset (state is %s)", self.get_state().name)

if have_bp_set == None:
if have_bp_set is None:
self.remove_breakpoint(reset_vec)
self.bp_manager.flush()
if borrowed_bp is not None:
self.set_breakpoint(borrowed_hp)
TRACE.debug("removed temporary breakpoint at 0x%08x", reset_vec)

# Make sure the thumb bit is set in XPSR in case the reset handler
Expand Down

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