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@Jchisholm204
Jchisholm204 committed Mar 5, 2024
1 parent bb2420a commit e9c92a3
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Showing 5 changed files with 33 additions and 2 deletions.
Binary file modified VCU/CAN.SchDoc
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Binary file modified VCU/MCU.SchDoc
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Binary file modified VCU/PCB.PcbDoc
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35 changes: 33 additions & 2 deletions VCU/VCU.PrjPcb
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Original file line number Diff line number Diff line change
Expand Up @@ -724,6 +724,13 @@ OutputJobsCount=0
ContentTypeGUID=CB6F2064-E317-11DF-B822-12313F0024A2
ConfigurationType=Source

[Generic_SimulationProfiles]
ActiveProfile=SOGDVCAJ
ProfileId0=SOGDVCAJ
ProfileName0=Mixed Sim Configuration
OutputType0=AdvSimNetlist
ConfigParameters0=Record=AdvSimNetlistView|SimulationName=Mixed Sim|OldCfgLoaded=True|DocumentPath=C:\Users\Jacob\Documents\GitHub\robocopyright\VCU\TOP.SchDoc|TF_Enabled=False|PZ_Enabled=False|Noise_Enabled=False|TRAN_FourierEnabled=False|SheetsToNetlist=0

[OutputGroup1]
Name=Netlist Outputs
Description=
Expand Down Expand Up @@ -848,7 +855,7 @@ OutputDefault1=0
Configuration1_Name1=ForceUpdateSettings
Configuration1_Item1=False
Configuration1_Name2=OutputConfigurationParameter1
Configuration1_Item2=Record=AdvSimNetlistView|SimulationName=Mixed Sim|ProfileId=KBBKBMSY|OldCfgLoaded=True|DocumentPath=C:\Users\Jacob\Documents\GitHub\robocopyright\VCU\TOP.SchDoc
Configuration1_Item2=Record=AdvSimNetlistView|SimulationName=Mixed Sim Configuration|OldCfgLoaded=True|DocumentPath=C:\Users\Jacob\Documents\GitHub\robocopyright\VCU\TOP.SchDoc|TF_Enabled=False|PZ_Enabled=False|Noise_Enabled=False|TRAN_FourierEnabled=False|SheetsToNetlist=0|ProfileId=SOGDVCAJ

[OutputGroup3]
Name=Documentation Outputs
Expand All @@ -860,7 +867,31 @@ OutputName1=Composite Drawing
OutputDocumentPath1=
OutputVariantName1=[No Variations]
OutputDefault1=0
PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1
PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.85|XCorrection=1.00|YCorrection=1.00|PrintKind=0|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=0|PaperKind=A3|PaperIndex=8
Configuration1_Name1=OutputConfigurationParameter1
Configuration1_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView|DocumentPath=C:\Users\Jacob\Documents\GitHub\QFSAE\pcb\VCU\PCB.PcbDoc
Configuration1_Name2=OutputConfigurationParameter2
Configuration1_Item2=IncludeBoardCutouts=False|IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False|DocumentPath=C:\Users\Jacob\Documents\GitHub\QFSAE\pcb\VCU\PCB.PcbDoc
Configuration1_Name3=OutputConfigurationParameter3
Configuration1_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\Jacob\Documents\GitHub\QFSAE\pcb\VCU\PCB.PcbDoc
Configuration1_Name4=OutputConfigurationParameter4
Configuration1_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\Jacob\Documents\GitHub\QFSAE\pcb\VCU\PCB.PcbDoc
Configuration1_Name5=OutputConfigurationParameter5
Configuration1_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=MidLayer1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\Jacob\Documents\GitHub\QFSAE\pcb\VCU\PCB.PcbDoc
Configuration1_Name6=OutputConfigurationParameter6
Configuration1_Item6=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\Jacob\Documents\GitHub\QFSAE\pcb\VCU\PCB.PcbDoc
Configuration1_Name7=OutputConfigurationParameter7
Configuration1_Item7=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=MidLayer2|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\Jacob\Documents\GitHub\QFSAE\pcb\VCU\PCB.PcbDoc
Configuration1_Name8=OutputConfigurationParameter8
Configuration1_Item8=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=MultiLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\Jacob\Documents\GitHub\QFSAE\pcb\VCU\PCB.PcbDoc
Configuration1_Name9=OutputConfigurationParameter9
Configuration1_Item9=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\Jacob\Documents\GitHub\QFSAE\pcb\VCU\PCB.PcbDoc
Configuration1_Name10=OutputConfigurationParameter10
Configuration1_Item10=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical4|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\Jacob\Documents\GitHub\QFSAE\pcb\VCU\PCB.PcbDoc
Configuration1_Name11=OutputConfigurationParameter11
Configuration1_Item11=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical5|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\Jacob\Documents\GitHub\QFSAE\pcb\VCU\PCB.PcbDoc
Configuration1_Name12=OutputConfigurationParameter12
Configuration1_Item12=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical13|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\Jacob\Documents\GitHub\QFSAE\pcb\VCU\PCB.PcbDoc
OutputType2=Harness Layout Drawing Print
OutputName2=Harness Layout Drawing Prints
OutputDocumentPath2=
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