Make sure no zero-bitsize connections appear

qualtran/bloqs/multiplexers/unary_iteration_bloq_test.py

@@ -41,7 +41,9 @@ def __init__(self, selection_bitsize: int, target_bitsize: int, control_bitsize:
 
     @cached_property
     def control_registers(self) -> Tuple[Register, ...]:
-        return (Register('control', QAny(self._control_bitsize)),)
+        return (
+            (Register('control', QAny(self._control_bitsize)),) if self._control_bitsize > 0 else ()
+        )
 
     @cached_property
     def selection_registers(self) -> Tuple[Register, ...]:
@@ -78,7 +80,7 @@ def test_unary_iteration_gate(selection_bitsize, target_bitsize, control_bitsize
         # Initial qubit values
         qubit_vals = {q: 0 for q in g.operation.qubits}
         # All controls 'on' to activate circuit
-        qubit_vals.update({c: 1 for c in g.quregs['control']})
+        qubit_vals.update({c: 1 for c in g.quregs.get('control', [])})
         # Set selection according to `n`
         qubit_vals.update(zip(g.quregs['selection'], QUInt(selection_bitsize).to_bits(n)))
 

qualtran/bloqs/state_preparation/state_preparation_via_rotation.py

@@ -178,17 +178,20 @@ def prga_prepare_amplitude(self) -> List['PRGAViaPhaseGradient']:
         if is_symbolic(self.state_coefficients):
             return [
                 PRGAViaPhaseGradient(
-                    self.state_bitsize,
-                    self.phase_bitsize,
-                    Shaped((slen(self.state_coefficients),)),
-                    self.control_bitsize + 1,
+                    selection_bitsize=self.state_bitsize,
+                    phase_bitsize=self.phase_bitsize,
+                    rom_values=Shaped((slen(self.state_coefficients),)),
+                    control_bitsize=self.control_bitsize + 1,
                 )
             ]
         ret = []
         ampl_rv, _ = self.rotation_tree.get_rom_vals()
         for qi in range(int(self.state_bitsize)):
             ctrl_rot_q = PRGAViaPhaseGradient(
-                qi, self.phase_bitsize, tuple(ampl_rv[qi]), self.control_bitsize + 1
+                selection_bitsize=qi,
+                phase_bitsize=self.phase_bitsize,
+                rom_values=tuple(ampl_rv[qi]),
+                control_bitsize=self.control_bitsize + 1,
             )
             ret.append(ctrl_rot_q)
         return ret
@@ -201,7 +204,10 @@ def prga_prepare_phases(self) -> 'PRGAViaPhaseGradient':
             else tuple(self.rotation_tree.get_rom_vals()[1])
         )
         return PRGAViaPhaseGradient(
-            self.state_bitsize, self.phase_bitsize, data_or_shape, self.control_bitsize + 1
+            selection_bitsize=self.state_bitsize,
+            phase_bitsize=self.phase_bitsize,
+            rom_values=data_or_shape,
+            control_bitsize=self.control_bitsize + 1,
         )
 
     def build_composite_bloq(self, bb: BloqBuilder, **soqs: SoquetT) -> Dict[str, SoquetT]:

qualtran/testing.py

@@ -37,6 +37,7 @@
 from qualtran._infra.data_types import check_dtypes_consistent, QDTypeCheckingSeverity
 from qualtran.drawing.musical_score import WireSymbol
 from qualtran.resource_counting import GeneralizerT
+from qualtran.symbolics import is_symbolic
 
 
 def assert_registers_match_parent(bloq: Bloq) -> CompositeBloq:
@@ -114,6 +115,11 @@ def assert_connections_compatible(cbloq: CompositeBloq):
         lr = cxn.left.reg
         rr = cxn.right.reg
 
+        if not is_symbolic(lr.dtype.num_qubits) and lr.dtype.num_qubits <= 0:
+            raise BloqError(f"{cxn} has an invalid number of qubits: {lr.dtype}")
+        if not is_symbolic(rr.dtype.num_qubits) and rr.dtype.num_qubits <= 0:
+            raise BloqError(f"{cxn} has an invalid number of qubits: {rr.dtype}")
+
         if not check_dtypes_consistent(lr.dtype, rr.dtype):
             raise BloqError(f"{cxn}'s QDTypes are incompatible: {lr.dtype} -> {rr.dtype}")