Tywaves update parametric workspace

Makefile

@@ -4,15 +4,23 @@ TYWAVES_SURFER_REPO=https://gitlab.com/rameloni/surfer-tywaves-demo.git
 TYWAVES_BRANCH=tywaves
 TYWAVES_NAME=surfer-tywaves-demo
 
-all: install-surfer-tywaves clean install-tywaves-backend
+CHISEL_FORK_REPO=https://github.com/rameloni/chisel.git
 
-install-surfer-tywaves:
+all: install-surfer-tywaves install-chisel-fork clean install-tywaves-backend
+
+create-tmp:
 	@mkdir -p tmp/
+
+install-surfer-tywaves: create-tmp
 	@cd tmp/ && git clone -b $(TYWAVES_BRANCH) $(TYWAVES_SURFER_REPO) && cd $(TYWAVES_NAME) && git submodule update --init --recursive
 	@cd tmp/$(TYWAVES_NAME) && cargo install --path .
 
 clean:
 	@rm -rf tmp/
 
+install-chisel-fork: create-tmp
+	@cd tmp/ && git clone $(CHISEL_FORK_REPO)
+	@cd tmp/chisel && sbt "unipublish / publishLocal"
+
 install-tywaves-backend:
 	@sbt publishLocal

README.md

@@ -53,6 +53,7 @@ The frontend will be installed as `surfer-tywaves` executable.
 ## Publish locally this scala project
 
 ```bash
+make install-chisel-fork
 make install-tywaves-backend
 ```
 

build.sbt

@@ -1,14 +1,16 @@
-val chiselVersion    = "6.1.0"
+val chiselVersion    = "6.1.0-tywaves-SNAPSHOT"
 val scalatestVersion = "3.2.16"
 val circeVersion     = "0.14.6"
 
-Compile / scalaSource := baseDirectory.value / "src/main"
+Compile / scalaSource := baseDirectory.value / "src/main/scala"
 
-Test / scalaSource := baseDirectory.value / "src/test"
+Test / scalaSource := baseDirectory.value / "src/test/scala"
 
 ThisBuild / organization := "com.github.rameloni"
 ThisBuild / version      := "0.1.0-SNAPSHOT"
-ThisBuild / scalaVersion := "2.13.10"
+ThisBuild / scalaVersion := "2.13.12"
+
+enablePlugins(ScalafmtPlugin)
 
 lazy val root = (project in file("."))
   .settings(
@@ -22,7 +24,12 @@ lazy val root = (project in file("."))
     libraryDependencies += "io.circe"          %% "circe-generic"        % circeVersion,
     libraryDependencies += "io.circe"          %% "circe-generic-extras" % "0.14.3",
     libraryDependencies += "io.circe"          %% "circe-parser"         % circeVersion,
-    libraryDependencies += "edu.berkeley.cs"   %% "chiseltest"           % "6.0.0",
+
+    libraryDependencies ++= Seq(
+      "com.typesafe.scala-logging" %% "scala-logging" % "3.9.5",
+      "ch.qos.logback" % "logback-classic" % "1.4.14"
+    ),
+
     scalacOptions ++= Seq(
       "-deprecation",
       "-encoding",

src/main/resources/logback.xml

@@ -0,0 +1,10 @@
+<configuration>
+    <appender name="STDOUT" class="ch.qos.logback.core.ConsoleAppender">
+        <encoder>
+            <pattern>%d{HH:mm:ss.SSS} [%thread] %-5level %logger{36} -%kvp- %msg%n</pattern>
+        </encoder>
+    </appender>
+    <root level="error">
+        <appender-ref ref="STDOUT"/>
+    </root>
+</configuration>

src/main/chisel3/tywaves/circuitparser/ChiselIRParser.scala → src/main/scala/chisel3/tywaves/circuitparser/ChiselIRParser.scala

@@ -3,11 +3,15 @@ package chisel3.tywaves.circuitparser
 import chisel3.experimental.{NoSourceInfo, SourceInfo, SourceLine}
 import chisel3.internal.firrtl.{ir => chiselIR}
 import chisel3.{Aggregate, Bundle, Data, Vec}
+import com.typesafe.scalalogging.Logger
 import tywaves.utils.UniqueHashMap
 import tywaves.circuitmapper.{Direction, ElId, HardwareType, Name, Type, tywaves_symbol_table}
 
 class ChiselIRParser
     extends CircuitParser[chiselIR.Circuit, chiselIR.Component, chiselIR.Port, Aggregate, Data, chiselIR.Command] {
+
+  private val logger = Logger(getClass.getName)
+
   // Collection of all modules in the circuit
   override lazy val modules        = new UniqueHashMap[ElId, (Name, chiselIR.Component)]()
   override lazy val ports          = new UniqueHashMap[ElId, (Name, Direction, Type /*, chiselIR.Port*/ )]()
@@ -33,12 +37,12 @@ class ChiselIRParser
 
     // Parse the internals of the module
     chiselComponent match {
-      case chiselIR.DefModule(_, moduleName, ports, body) =>
+      case chiselIR.DefModule(_, moduleName, _, _, ports, body) =>
         ports.foreach(parsePort(name, _, moduleName))
         // TODO: Parse the body:
         body.foreach(parseBodyStatement(name, _, moduleName))
       case chiselIR.DefBlackBox(_, name, ports, topDir, params) =>
-        println(s"DefBlackBox: name: $name, ports: $ports, topDir: $topDir, params: $params")
+        logger.debug(s"DefBlackBox: name: $name, ports: $ports, topDir: $topDir, params: $params")
 
       case _ => throw new Exception(s"Failed to parse module $name. Unknown type.")
     }
@@ -76,7 +80,6 @@ class ChiselIRParser
     portData match {
       case agg: Aggregate =>
         // TODO: check this
-        println(s"AggregateType: $agg")
         parseAggregate(
           elId,
           Name(name, scope, parentModule),
@@ -120,7 +123,6 @@ class ChiselIRParser
       case b: Bundle =>
         b.elements.foreach { case (fieldName, dataType) =>
           parseElement(elId, Name(fieldName, name.name, parentModule), dir, hwType, dataType, parentModule)
-          println(s"AggregateType: $aggrType, dir: $dir, hwType: $hwType, name: $name")
 
           val variable = tywaves_symbol_table.Variable(
             name.name,
@@ -175,15 +177,15 @@ class ChiselIRParser
       case chiselIR.DefRegInit(sourceInfo, dataType, _, _, _) =>
         Some((sourceInfo, dataType, HardwareType("Register", Some(dataType.getWidth))))
 
-      case _: chiselIR.Connect      => Console.err.println("ChiselIRParser: Parsing Connect. Skip."); None
-      case _: chiselIR.DefPrim[?]   => Console.err.println("ChiselIRParser: Parsing DefPrim. Skip."); None
-      case _: chiselIR.WhenBegin    => Console.err.println("ChiselIRParser: Parsing WhenBegin. Skip."); None
-      case _: chiselIR.WhenEnd      => Console.err.println("ChiselIRParser: Parsing WhenEnd. Skip."); None
-      case _: chiselIR.Printf       => Console.err.println("ChiselIRParser: Parsing Printf. Skip."); None
-      case _: chiselIR.AltBegin     => Console.err.println("ChiselIRParser: Parsing AltBegin. Skip."); None
-      case _: chiselIR.OtherwiseEnd => Console.err.println("ChiselIRParser: Parsing OtherwiseEnd. Skip."); None
+      case _: chiselIR.Connect      => logger.debug("ChiselIRParser: Parsing Connect. Skip."); None
+      case _: chiselIR.DefPrim[?]   => logger.debug("ChiselIRParser: Parsing DefPrim. Skip."); None
+      case _: chiselIR.WhenBegin    => logger.debug("ChiselIRParser: Parsing WhenBegin. Skip."); None
+      case _: chiselIR.WhenEnd      => logger.debug("ChiselIRParser: Parsing WhenEnd. Skip."); None
+      case _: chiselIR.Printf       => logger.debug("ChiselIRParser: Parsing Printf. Skip."); None
+      case _: chiselIR.AltBegin     => logger.debug("ChiselIRParser: Parsing AltBegin. Skip."); None
+      case _: chiselIR.OtherwiseEnd => logger.debug("ChiselIRParser: Parsing OtherwiseEnd. Skip."); None
       case a =>
-        println(s"a a a: $a")
+        logger.error(s"Match case not covered: $a")
         None
         ???
     }
@@ -209,7 +211,7 @@ class ChiselIRParser
   def createId(info: SourceInfo, specialPort: Option[String] = None): ElId =
     info match {
       case _: NoSourceInfo =>
-        println(Console.RED + "Warning: Bad ID NoSourceInfo" + Console.RESET)
+        logger.debug("Warning: Bad ID NoSourceInfo")
         ElId(specialPort.getOrElse("NoInfo"), 0, 0)
       case SourceLine(source, row, col) =>
         ElId(source, row, col, specialPort.getOrElse(""))

src/main/chisel3/tywaves/circuitparser/FirrtlIRParser.scala → src/main/scala/chisel3/tywaves/circuitparser/FirrtlIRParser.scala

@@ -1,8 +1,9 @@
 package chisel3.tywaves.circuitparser
 
+import com.typesafe.scalalogging.Logger
 import firrtl.{ir => firrtlIR}
 import tywaves.utils.UniqueHashMap
-import tywaves.circuitmapper.{ElId, Name, Direction, Type, HardwareType}
+import tywaves.circuitmapper.{Direction, ElId, HardwareType, Name, Type}
 
 class FirrtlIRParser
     extends CircuitParser[
@@ -13,6 +14,9 @@ class FirrtlIRParser
       firrtlIR.Type,
       firrtlIR.Statement,
     ] {
+
+  private val logger = Logger(getClass.getName)
+
   // Collection of all modules in the circuit
   override lazy val modules        = new UniqueHashMap[ElId, (Name, firrtlIR.DefModule)]()
   override lazy val ports          = new UniqueHashMap[ElId, (Name, Direction, Type /*, firrtlIR.Port*/ )]()
@@ -33,12 +37,12 @@ class FirrtlIRParser
 
     // Parse the internals of the module
     firrtlModule match {
-      case firrtlIR.Module(_, moduleName, ports, body) =>
+      case firrtlIR.Module(_, moduleName, _, _, ports, body) =>
         ports.foreach(parsePort(name, _, moduleName))
         // TODO: Parse the body:
         parseBodyStatement(name, body, moduleName)
       case firrtlIR.ExtModule(_, name, ports, defname, params) =>
-        println(s"ExtModule: name: $name, ports: $ports, defname: $defname, params: $params")
+        logger.debug(s"ExtModule: name: $name, ports: $ports, defname: $defname, params: $params")
 
       case _ => throw new Exception(s"Failed to parse module $name. Unknown type.")
     }
@@ -58,7 +62,6 @@ class FirrtlIRParser
     // Parse the type to build flattened ports
     firrtlType match {
       case agg: firrtlIR.AggregateType =>
-        println(s"AggregateType: $agg")
         parseAggregate(
           elId,
           Name(name, scope, parentModule),
@@ -173,11 +176,11 @@ class FirrtlIRParser
           parentModule,
         )
 
-      case _: Connect       => Console.err.println("FirrtlIR parser: Parsing Connect. Skip.")
-      case _: DefNode       => Console.err.println("FirrtlIR parser: Parsing DefNode. Skip.")
-      case _: Conditionally => Console.err.println("FirrtlIR parser: Parsing Conditionally. Skip.")
+      case _: Connect       => logger.debug("FirrtlIR parser: Parsing Connect. Skip.")
+      case _: DefNode       => logger.debug("FirrtlIR parser: Parsing DefNode. Skip.")
+      case _: Conditionally => logger.debug("FirrtlIR parser: Parsing Conditionally. Skip.")
       case a => // TODO: other cases to be implemented
-        println("aaa: " + a)
+        logger.error(s"Match case not covered: $a")
         ???
     }
   }
@@ -188,7 +191,7 @@ class FirrtlIRParser
   def createId(info: firrtlIR.Info, specialPort: Option[String] = None): ElId =
     info match {
       case firrtlIR.NoInfo =>
-        println(Console.RED + "Warning: Bad ID NoInfo" + Console.RESET)
+        logger.debug("Warning: Bad ID NoInfo")
         ElId(specialPort.getOrElse("NoInfo"), 0, 0)
       case f: firrtlIR.FileInfo =>
         val (source, row, col) = f.split