Tywaves-chisel v0.1.0-demo

The first version of the Tywaves-chisel backend demo. It provides functionality to associate high-level information of Chisel source code with the trace files emitted by Chiselsim.

What's Changed

• Migrate from Chiseltest to Chiselsim by @rameloni in fa8860a
• Create an ephemeral simulator to emit VCD traces with Chiselsim by @rameloni in 166f770
• Add support to access and parse Chisel IR by @rameloni in b0236fb
• Add support to access and parse Chisel IR by @rameloni in d610c59
• Map Chisel IR with Firrtl IR element by element by @rameloni in e75f5f4
• Parse the HGLDD file and map to Firrtl IR by @rameloni in 5b480dd and ee4da3a
• Create a wrapper of SingleBackendSimulator and ChiselWorkspace to use the "-g" option for simulation with verilator by @rameloni in 2c166b9
• Emit the tywaves state file and fic issues by @rameloni in e9f0856, 7ba56a8, 608af4e, 048f999, ae8458e, eac296c, 456afaa, 5a47163 and 91ca2fd
• Automatically launch Tywaves-surfer from Chiselsim by @rameloni in 088fcd9

Full Changelog: https://github.com/rameloni/tywaves-chisel-demo/commits/v0.1.0-SNAPSHOT