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Cache Memory design- The Design involves 4 way set associative data cache, 2 way set associative instruction cache with LRU replacement policy. The Design uses MESI protocol to maintain cache coherence.

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rashmi-kulkarni10/cache-design

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Final Project Report .pdf
Final Project Report .pdf
 
 
cache.c
cache.c
 
 
cache.h
cache.h
 
 
main.c
main.c
 
 
makefile
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Cache Memory design- The Design involves 4 way set associative data cache, 2 way set associative instruction cache with LRU replacement policy. The Design uses MESI protocol to maintain cache coherence.

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