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Update uctags.vim (preservim#887)
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* Update uctags.vim

Add for systemverilog.  Accdording to https://docs.ctags.io/en/latest/man/ctags-lang-verilog.7.html

* Update autoload/tagbar/types/uctags.vim

Incorporating review comments as per note from submitter

---------

Co-authored-by: David Hegland <darth.gerbil@gmail.com>
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@sqlmap3 @raven42
sqlmap3 and raven42 authored Jul 24, 2024
1 parent 0815b54 commit 1690b19
Showing 1 changed file with 47 additions and 0 deletions.
47 changes: 47 additions & 0 deletions autoload/tagbar/types/uctags.vim
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Original file line number Diff line number Diff line change
Expand Up @@ -1332,6 +1332,53 @@ function! tagbar#types#uctags#init(supported_types) abort
\ {'short' : 't', 'long' : 'tasks', 'fold' : 0, 'stl' : 1}
\ ]
let types.verilog = type_verilog
" SystemVerilog {{{1
let type_systemverilog = tagbar#prototypes#typeinfo#new()
let type_systemverilog.ctagstype = 'systemverilog'
let type_systemverilog.kinds = [
\ {'short' : 'A', 'long' : 'assertions', 'fold' : 0, 'stl' : 1},
\ {'short' : 'C', 'long' : 'class', 'fold' : 0, 'stl' : 1},
\ {'short' : 'E', 'long' : 'enum', 'fold' : 0, 'stl' : 1},
\ {'short' : 'H', 'long' : 'checkers', 'fold' : 0, 'stl' : 1},
\ {'short' : 'I', 'long' : 'interfaces', 'fold' : 0, 'stl' : 1},
\ {'short' : 'K', 'long' : 'packages', 'fold' : 1, 'stl' : 0},
\ {'short' : 'L', 'long' : 'clokcing', 'fold' : 0, 'stl' : 1},
\ {'short' : 'M', 'long' : 'modports', 'fold' : 0, 'stl' : 1},
\ {'short' : 'N', 'long' : 'nettype', 'fold' : 0, 'stl' : 0},
\ {'short' : 'O', 'long' : 'constraints', 'fold' : 0, 'stl' : 1},
\ {'short' : 'P', 'long' : 'programs', 'fold' : 0, 'stl' : 1},
\ {'short' : 'Q', 'long' : 'prototypes', 'fold' : 0, 'stl' : 1},
\ {'short' : 'R', 'long' : 'properties', 'fold' : 0, 'stl' : 1},
\ {'short' : 'S', 'long' : 'structs and unions', 'fold' : 0, 'stl' : 1},
\ {'short' : 'T', 'long' : 'type declarations', 'fold' : 0, 'stl' : 1},
\ {'short' : 'V', 'long' : 'covergroups', 'fold' : 0, 'stl' : 1},
\ {'short' : 'b', 'long' : 'blocks', 'fold' : 0, 'stl' : 1},
\ {'short' : 'c', 'long' : 'constants', 'fold' : 0, 'stl' : 0},
\ {'short' : 'd', 'long' : 'text macros', 'fold' : 0, 'stl' : 1},
\ {'short' : 'e', 'long' : 'events', 'fold' : 0, 'stl' : 1},
\ {'short' : 'f', 'long' : 'functions', 'fold' : 0, 'stl' : 1},
\ {'short' : 'i', 'long' : 'module or interface', 'fold' : 0, 'stl' : 1},
\ {'short' : 'l', 'long' : 'interface class', 'fold' : 0, 'stl' : 1},
\ {'short' : 'm', 'long' : 'module', 'fold' : 0, 'stl' : 1},
\ {'short' : 'n', 'long' : 'net data types', 'fold' : 0, 'stl' : 0},
\ {'short' : 'p', 'long' : 'ports', 'fold' : 1, 'stl' : 1},
\ {'short' : 'q', 'long' : 'sequences', 'fold' : 0, 'stl' : 1},
\ {'short' : 'r', 'long' : 'variable data types', 'fold' : 1, 'stl' : 1},
\ {'short' : 't', 'long' : 'tasks', 'fold' : 0, 'stl' : 1},
\ {'short' : 'w', 'long' : 'members', 'fold' : 0, 'stl' : 1}
\ ]
let type_systemverilog.sro = '.' " Nesting doesn't seem to be possible
let type_systemverilog.kind2scope = {
\ 'E' : 'enum',
\ 'C' : 'class',
\ 'm' : 'module',
\ }
let type_systemverilog.scope2kind = {
\ 'enum' : 'E',
\ 'class' : 'C',
\ 'module' : 'm',
\ }
let types.systemverilog = type_systemverilog
" VHDL {{{1
" The VHDL ctags parser unfortunately doesn't generate proper scopes
let type_vhdl = tagbar#prototypes#typeinfo#new()
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