Educational RISC-V 32I simulator with focus not on performance but on understanding the architecture and hardware.
- Loading/Run a rv32i elf executable (with some special compile options)
- SerialPort simulation simple char output
- all rv32i instructions
- machine mode only
- exceptions and interrupts
- CSR registers
- Hardware timer & interrupt
- Hardware timer pending reset (currently target software reset)
- many RO / RW CSR constrains
- supervisor and user modes
- A and M extension instructions
- better (graphical) device options
My goal is to develop a good to understand and expandable simulation. That can run a simple embedded like OS. And maybe even dynamically load rv32i executables into this running and simulated hardware and OS.
- riscv-gnu-toolchain (newlib arch=rv32i) (https://github.com/riscv/riscv-gnu-toolchain)
- libelf