Skip to content

Commit

Permalink
[LLVM][XTHeadVector] Implement intrinsics for vmacc/vnmsac/vmadd/vnms…
Browse files Browse the repository at this point in the history 
…ub. (llvm#66)

* [LLVM][XTHeadVector] Define intrinsics.

* [LLVM][XTHeadVector] Define pseudos and pats.

* [LLVM][XTHeadVector] Add test cases.

* [NFC][XTHeadVector] Update README.
  • Loading branch information
@AinsleySnow @RevySR
AinsleySnow authored and RevySR committed Apr 3, 2024
1 parent ba3bbf1 commit bb218ee
Show file tree
Hide file tree
Showing 7 changed files with 7,882 additions and 0 deletions.
1 change: 1 addition & 0 deletions README.md
View file
Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,7 @@ Any feature not listed below but present in the specification should be consider
- (Done) `12.8. Vector Integer Min/Max Instructions`
- (Done) `12.10. Vector Integer Divide Instructions`
- (Done) `12.11. Vector Widening Integer Multiply Instructions`
- (Done) `12.12. Vector Single-Width Integer Multiply-Add Instructions`
- (WIP) Clang intrinsics related to the `XTHeadVector` extension:
- (WIP) `6. Configuration-Setting and Utility`
- (Done) `6.1. Set vl and vtype`
Expand Down
32 changes: 32 additions & 0 deletions llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -612,6 +612,27 @@ let TargetPrefix = "riscv" in {
let VLOperand = 4;
}

// UnMasked Vector Multiply-Add operations, its first operand can not be undef.
// Input: (vector_in, vector_in/scalar, vector_in, vl)
class XVTernaryAAXAUnMasked
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_any_ty, LLVMMatchType<0>,
llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic {
let ScalarOperand = 1;
let VLOperand = 3;
}

// Masked Vector Multiply-Add operations, its first operand can not be undef.
// Input: (vector_in, vector_in/scalar, vector_in, mask, vl)
class XVTernaryAAXAMasked
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_any_ty, LLVMMatchType<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic {
let ScalarOperand = 1;
let VLOperand = 4;
}

multiclass XVBinaryAAX {
def "int_riscv_" # NAME : RISCVBinaryAAXUnMasked;
def "int_riscv_" # NAME # "_mask" : XVBinaryAAXMasked;
Expand All @@ -631,6 +652,11 @@ let TargetPrefix = "riscv" in {
def "int_riscv_" # NAME : RISCVBinaryABShiftUnMasked;
def "int_riscv_" # NAME # "_mask" : XVBinaryABShiftMasked;
}

multiclass XVTernaryAAXA {
def "int_riscv_" # NAME : XVTernaryAAXAUnMasked;
def "int_riscv_" # NAME # "_mask" : XVTernaryAAXAMasked;
}
}

let TargetPrefix = "riscv" in {
Expand Down Expand Up @@ -698,6 +724,12 @@ let TargetPrefix = "riscv" in {
defm th_vwmul : XVBinaryABX;
defm th_vwmulu : XVBinaryABX;
defm th_vwmulsu : XVBinaryABX;

// 12.12. Vector Single-Width Integer Multiply-Add Instructions
defm th_vmacc : XVTernaryAAXA;
defm th_vnmsac : XVTernaryAAXA;
defm th_vmadd : XVTernaryAAXA;
defm th_vnmsub : XVTernaryAAXA;
} // TargetPrefix = "riscv"

let TargetPrefix = "riscv" in {
Expand Down
101 changes: 101 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1584,6 +1584,23 @@ class XVPseudoTiedBinaryMask<VReg RetClass,
let IsTiedPseudo = 1;
}

class XVPseudoBinaryMaskNoPolicy<VReg RetClass,
RegisterClass Op1Class,
DAGOperand Op2Class,
string Constraint> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge,
Op1Class:$rs2, Op2Class:$rs1,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = !interleave([Constraint, "$rd = $merge"], ",");
let HasVLOp = 1;
let HasSEWOp = 1;
}

multiclass XVPseudoBinary<VReg RetClass,
VReg Op1Class,
DAGOperand Op2Class,
Expand Down Expand Up @@ -1612,6 +1629,20 @@ multiclass XVPseudoTiedBinary<VReg RetClass,
}
}

multiclass XVPseudoTernaryNoPolicy<VReg RetClass,
RegisterClass Op1Class,
DAGOperand Op2Class,
LMULInfo MInfo,
string Constraint = "",
bit Commutable = 0> {
let VLMul = MInfo.value in {
let isCommutable = Commutable in
def "_" # MInfo.MX : VPseudoTernaryNoMask<RetClass, Op1Class, Op2Class, Constraint>;
def "_" # MInfo.MX # "_MASK" : XVPseudoBinaryMaskNoPolicy<RetClass, Op1Class, Op2Class, Constraint>,
RISCVMaskedPseudo<MaskIdx=3>;
}
}

multiclass XVPseudoBinaryV_VV<LMULInfo m, string Constraint = "", int sew = 0> {
defm _VV : XVPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint, sew>;
}
Expand Down Expand Up @@ -1667,6 +1698,16 @@ multiclass XVPseudoBinaryVNSHT_VI<LMULInfo m> {
!if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
}

multiclass XVPseudoTernaryV_VV_AAXA<LMULInfo m, string Constraint = ""> {
defm _VV : XVPseudoTernaryNoPolicy<m.vrclass, m.vrclass, m.vrclass, m,
Constraint, Commutable=1>;
}

multiclass XVPseudoTernaryV_VX_AAXA<LMULInfo m, string Constraint = ""> {
defm _VX : XVPseudoTernaryNoPolicy<m.vrclass, GPR, m.vrclass, m,
Constraint, Commutable=1>;
}

multiclass XVPseudoVALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
foreach m = MxListXTHeadV in {
defvar mx = m.MX;
Expand Down Expand Up @@ -1961,6 +2002,23 @@ multiclass XVPseudoVWMUL_VV_VX {
}
}

multiclass XVPseudoVMAC_VV_VX_AAXA<string Constraint = ""> {
foreach m = MxListXTHeadV in {
defvar mx = m.MX;
defvar WriteVIMulAddV_MX = !cast<SchedWrite>("WriteVIMulAddV_" # mx);
defvar WriteVIMulAddX_MX = !cast<SchedWrite>("WriteVIMulAddX_" # mx);
defvar ReadVIMulAddV_MX = !cast<SchedRead>("ReadVIMulAddV_" # mx);
defvar ReadVIMulAddX_MX = !cast<SchedRead>("ReadVIMulAddX_" # mx);

defm "" : XVPseudoTernaryV_VV_AAXA<m, Constraint>,
Sched<[WriteVIMulAddV_MX, ReadVIMulAddV_MX, ReadVIMulAddV_MX,
ReadVIMulAddV_MX, ReadVMask]>;
defm "" : XVPseudoTernaryV_VX_AAXA<m, Constraint>,
Sched<[WriteVIMulAddX_MX, ReadVIMulAddV_MX, ReadVIMulAddV_MX,
ReadVIMulAddX_MX, ReadVMask]>;
}
}

//===----------------------------------------------------------------------===//
// Helpers to define the intrinsic patterns for the XTHeadVector extension.
//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -2331,6 +2389,27 @@ multiclass XVPseudoVMINMAX_VV_VX {
}
}

multiclass XVPatTernaryV_VV_AAXA<string intrinsic, string instruction,
list<VTypeInfo> vtilist> {
foreach vti = vtilist in
let Predicates = GetXVTypePredicates<vti>.Predicates in
defm : VPatTernary<intrinsic, instruction, "VV",
vti.Vector, vti.Vector, vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass,
vti.RegClass, vti.RegClass>;
}

multiclass XVPatTernaryV_VX_AAXA<string intrinsic, string instruction,
list<VTypeInfo> vtilist> {
foreach vti = vtilist in
let Predicates = GetXVTypePredicates<vti>.Predicates in
defm : VPatTernary<intrinsic, instruction,
"V"#vti.ScalarSuffix,
vti.Vector, vti.Scalar, vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass,
vti.ScalarRegClass, vti.RegClass>;
}

multiclass XVPatBinaryV_VV_VX_VI<string intrinsic, string instruction,
list<VTypeInfo> vtilist, Operand ImmType = simm5>
: XVPatBinaryV_VV<intrinsic, instruction, vtilist>,
Expand Down Expand Up @@ -2397,6 +2476,11 @@ multiclass XVPatBinaryM_VX_VI<string intrinsic, string instruction,
: XVPatBinaryM_VX<intrinsic, instruction, vtilist>,
XVPatBinaryM_VI<intrinsic, instruction, vtilist>;

multiclass XVPatTernaryV_VV_VX_AAXA<string intrinsic, string instruction,
list<VTypeInfo> vtilist>
: XVPatTernaryV_VV_AAXA<intrinsic, instruction, vtilist>,
XVPatTernaryV_VX_AAXA<intrinsic, instruction, vtilist>;

//===----------------------------------------------------------------------===//
// 12.1. Vector Single-Width Saturating Add and Subtract
//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -2674,6 +2758,23 @@ let Predicates = [HasVendorXTHeadV] in {
defm : XVPatBinaryW_VV_VX<"int_riscv_th_vwmulsu", "PseudoTH_VWMULSU", AllWidenableIntXVectors>;
} // Predicates = [HasVendorXTHeadV]

//===----------------------------------------------------------------------===//
// 12.12. Vector Single-Width Integer Multiply-Add Instructions
//===----------------------------------------------------------------------===//
let Predicates = [HasVendorXTHeadV] in {
defm PseudoTH_VMACC : XVPseudoVMAC_VV_VX_AAXA;
defm PseudoTH_VNMSAC : XVPseudoVMAC_VV_VX_AAXA;
defm PseudoTH_VMADD : XVPseudoVMAC_VV_VX_AAXA;
defm PseudoTH_VNMSUB : XVPseudoVMAC_VV_VX_AAXA;
} // Predicates = [HasVendorXTHeadV]

let Predicates = [HasVendorXTHeadV] in {
defm : XVPatTernaryV_VV_VX_AAXA<"int_riscv_th_vmadd", "PseudoTH_VMADD", AllIntegerXVectors>;
defm : XVPatTernaryV_VV_VX_AAXA<"int_riscv_th_vnmsub", "PseudoTH_VNMSUB", AllIntegerXVectors>;
defm : XVPatTernaryV_VV_VX_AAXA<"int_riscv_th_vmacc", "PseudoTH_VMACC", AllIntegerXVectors>;
defm : XVPatTernaryV_VV_VX_AAXA<"int_riscv_th_vnmsac", "PseudoTH_VNMSAC", AllIntegerXVectors>;
} // Predicates = [HasVendorXTHeadV]

//===----------------------------------------------------------------------===//
// 12.14. Vector Integer Merge and Move Instructions
//===----------------------------------------------------------------------===//
Expand Down
Loading

0 comments on commit bb218ee

Please sign in to comment.