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Add citation for Smstateen (#73)
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AoteJin authored Dec 13, 2024
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2 changes: 1 addition & 1 deletion chapter2.adoc
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@@ -226,7 +226,7 @@ The `nmip`, `mprven`, `stoptime`, `stopcount`, `ebreakm` and `cetrig` fields in

==== Extension of Sdtrig CSR

The Smtdeleg cite:[smtdeleg] and Smstateen extensions define the process for delegating triggers to modes with lower privilege than M-mode. The Sdsec requires both extensions to securely delegate Sdtrig triggers to supervisor domain.
The Smtdeleg cite:[smtdeleg] and Smstateen cite:[smstateen] extensions define the process for delegating triggers to modes with lower privilege than M-mode. The Sdsec requires both extensions to securely delegate Sdtrig triggers to supervisor domain.

[NOTE]
When M-mode enables debugging for supervisor domain, it can optionally delegate the triggers to the supervisor domain, allowing an external debugger with S-mode privilege to configure these triggers.
5 changes: 5 additions & 0 deletions example.bib
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@@ -31,4 +31,9 @@ @electronic{worldguard
@electronic{smtdeleg,
title = {RISC-V Trigger Delegation Specification},
url = {https://github.com/riscv/ft-trigger-delegation}
}

@electronic{smstateen,
title = {RISC-V State Enable Extension},
url = {https://github.com/riscvarchive/riscv-state-enable}
}
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2 changes: 1 addition & 1 deletion intro.adoc
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@@ -12,7 +12,7 @@ A summary of the changes introduced by _The RISC-V External Debug Security Speci
- *Non-secure debug:* Add a non-secure debug state to relax security constraints.
- *Debug Mode entry:* An external debugger can only halt the hart and enter debug mode when debug is allowed in current privilege mode.
- *Memory Access:* Memory access from a hart’s point of view, using the Program Buffer or an Abstract Command, must be checked by the hart's memory protection mechanisms as if the hart is running at <<dbgaccpriv, debug access privilege level>>; memory access from the Debug Module using System Bus Access must be checked by a system memory protection mechanism, such as IOPMP or WorldGuard.
- *Register Access:* Register access using the Program Buffer or an Abstract Command works as if the hart is running at <<dbgaccpriv, debug access privilege level>> instead of M-mode privilege level. The debug CSRs (`dcsr` and `dpc` ) are shadowed in supervisor domains while Smtdeleg cite:[smtdeleg] and Smstateen cite:[smtdeleg] extensions expose the trigger CSRs to supervisor domains.
- *Register Access:* Register access using the Program Buffer or an Abstract Command works as if the hart is running at <<dbgaccpriv, debug access privilege level>> instead of M-mode privilege level. The debug CSRs (`dcsr` and `dpc` ) are shadowed in supervisor domains while Smtdeleg cite:[smtdeleg] and Smstateen cite:[smstateen] extensions expose the trigger CSRs to supervisor domains.
- *Triggers:* Triggers (with action=1) can only fire or match when external debug is allowed in the current privilege mode.

=== Terminology

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