Merge pull request #40 from ved-rivos/issue_34

Enable delegation of any-supervisor-domain-external-interrupt-pending

chapter7.adoc

@@ -211,16 +211,26 @@ that cause a M-level supervisor domain external interrupt. The enable bits in
 `msdeie` do not affect the S- and VS-level external interrupt pending signals
 from the interrupt controller selected by `msdcfg.SDICN`.
 
-=== Machine Interrupt registers (`mip` and `mie`)
-
-The `Smsdia` extension introduces the machine supervisor domain external
-interrupt-pending (`MSDEIP` - bit 32) field in `mip` and the machine supervisor
-domain external interrupt-enable (`MSDEIE` - bit 32) field in `mie`. The
-`MSDEIP` bit is read-only, and is 1 if and only if the bitwise logical AND of
-CSRs `msdeip` and `msdeie` is nonzero in any bit.
-
-Multiple simultaneous interrupts destined for M-mode are handled in the
-following decreasing priority order: MEI, MSI, MTI, MSDEI, SEI, SSI, STI.
+=== Machine and Supervisor Interrupt registers (`mip/mie` and `sip/sie`)
+
+The `Smsdia` extension introduces the local supervisor domain external
+interrupt-pending (`LSDEI`). This interrupt is treated as a standard local
+interrupt that is assigned to bit 16 in the `mip`, `mie`, `sip`, and `sie`
+registers. The bit 16 in `mip` and `sip` is called `LSDEIP` and the same bit in
+`mie` and `sie` is called `LSDEIE`. The `mideleg` register controls the
+delegation of `LSDEI` interrupt to S-mode. This interrupt cannot be delegated to
+VS-mode and the the bit 16 of `hideleg` is read-only zero.
+
+The `mip.LSDEIP` bit is read-only, and is 1 if and only if the bitwise logical
+AND of CSRs `msdeip` and `msdeie` is nonzero in any bit. The `sip.LSDEIP` bit is
+read-only, and is 0 if `LSDEI` is not delegated to S-mode otherwise it returns
+the value of the `mip.LSDEIP` when read.
+
+Multiple simultaneous interrupts destined for different privilege modes are
+handled in decreasing order of destined privilege mode. Multiple simultaneous
+interrupts destined for the same privilege mode are handled in the following
+decreasing priority order: high-priority RAS event, MEI, MSI, MTI, SEI, SSI,
+STI, LSDEI, SGEI, VSEI, VSSI, VSTI, LCOFI, low-priority RAS event.
 
 [NOTE]
 ====
@@ -230,4 +240,12 @@ supervisor domain that has a supervisor domain interrupt controller directly
 assigned to it, the RDSM updates the `msdcfg.SDICN` to select that interrupt
 controller and may clear the bit corresponding to that interrupt controller in
 `msdeie` prior to resuming execution of the supervisor domain.
+
+The RDSM may delegate `LSDEI` to a supervisor domain that may be entrusted by
+the RDSM to get notified about supervisor domain external interrupts pending for
+one or more other supervisor domains. Typically, this use case involves a single
+supervisor domain that is trusted by the RDSM to receive such notifications. The
+delegation supports optimizing the exit sequence from such supervisor domain by
+enabling such supervisor domains to voluntarily yield execution in response to
+pending interrupts for the other supervisor domains.
 ====