Merge pull request #3 from riscv/tweaks

Various non-normative improvements

contributors.adoc

@@ -4,4 +4,3 @@ This RISC-V specification has been contributed to directly or indirectly by:
 
 [%hardbreaks]
 * Dr. Philipp Tomsich <philipp.tomsich@vrull.eu>
-* Author2 <required2@email.com>

header.adoc

@@ -1,5 +1,5 @@
 [[header]]
-:description: RISC-V Integer Conditional (ZiCond) operations extension
+:description: RISC-V Integer Conditional (Zicond) operations extension
 :company: RISC-V.org
 :revdate: 9/2022
 :revnumber: 1.0
@@ -36,7 +36,7 @@ endif::[]
 :footnote:
 :xrefstyle: short
 
-= RISC-V Integer Conditional (ZiCond) operations extension
+= RISC-V Integer Conditional (Zicond) operations extension
 Dr. Philipp Tomsich (VRULL GmbH)
 
 // Preamble

intro.adoc

@@ -1,14 +1,14 @@
 [[intro]]
 == Introduction
-The ZiCondOps extension defines provides a simple solution that provides most of the benefit and all of the flexibility one would desire to support conditional arithmetic and conditional-select/move operations, while remaining true to the RISC-V design philosophy.
-The instructions follow the format for R-type instructions with 3 operands (i.e., 2 source operands and 1 destinantion operand).
-Using these instructions, branchless sequences can be implemented (typically in two-instruction sequenes) without the need for instruction fusion, special provisions during the decoding of architectural instrucitons, or other microarchitectural provisions.
+The Zicond extension defines provides a simple solution that provides most of the benefit and all of the flexibility one would desire to support conditional arithmetic and conditional-select/move operations, while remaining true to the RISC-V design philosophy.
+The instructions follow the format for R-type instructions with 3 operands (i.e., 2 source operands and 1 destination operand).
+Using these instructions, branchless sequences can be implemented (typically in two-instruction sequences) without the need for instruction fusion, special provisions during the decoding of architectural instructions, or other microarchitectural provisions.
 
 === Suitability for Fast Track Extension Process
 This proposed extension meets the Fast Track criteria: it consists of two, simple R-form instructions, it addresses a wide range of use-cases for branchless sequences, it composes with the existing RISC-V instruction set, and is not expected to be contentious.
 
 === Motivation and use cases
-One of the shortcoming of RISC-V, compared to competing instruction set architectures, is the absence of conditional operations to support branchless code-generation: this includes conditional arithmetic, conditional select and conditional move operations.
+One of the shortcomings of RISC-V, compared to competing instruction set architectures, is the absence of conditional operations to support branchless code-generation: this includes conditional arithmetic, conditional select and conditional move operations.
 The design principles or RISC-V (e.g. the absence of an instruction-format that supports 3 source registers and an output register) make it unlikely that direct equivalents of the competing instructions will be introduced.
 
 Yet, low-cost conditional instructions are a desirable feature as they allow the replacement of branches in a broad range of suitable situations (whether the branch turns out to be unpredictable or predictable) so as to reduce the capacity and aliasing pressures on BTBs and branch predictors, and to allow for longer basic blocks (for both the hardware and the compiler to work with).

zicondops.adoc

@@ -1,11 +1,11 @@
-[[ZiCond]]
-== ZiCond proposed specification
+[[Zicond]]
+== Zicond proposed specification
 
 The "Conditional" operations extension provides a simple solution that provides most of the benefit and all of the flexibility one would desire to support conditional arithmetic and conditional-select/move operations, while remaining true to the RISC-V design philosophy.
 The instructions follow the format for R-type instructions with 3 operands (i.e., 2 source operands and 1 destination operand).
-Using these instructions, branchless sequences can be implemented (typically in two-instruction sequences) without the need for instruction fusion, special provisions during the decoding of architectural instrucitons, or other microarchitectural provisions.
+Using these instructions, branchless sequences can be implemented (typically in two-instruction sequences) without the need for instruction fusion, special provisions during the decoding of architectural instructions, or other microarchitectural provisions.
 
-The following instructions comprise the ZiCond extension:
+The following instructions comprise the Zicond extension:
 
 [%header,cols="^1,^1,4,8"]
 |===
@@ -44,12 +44,12 @@ Based on these two instructions, synthetic instructions (i.e., short instruction
 * conditional bitwise-xor, if zero
 * conditional bitwise-xor, if non-zero
 
-Additionally, the following *conditional select* intructions are supported:
+Additionally, the following *conditional select* instructions are supported:
 
 * conditional-select, if zero
 * conditional-select, if non-zero
 
-More complex conditions, such as comparisons against immediates, registers, single-bit tests, comparisons against ranges, etc. can be realised by composing these new instructions with existing instructions.
+More complex conditions, such as comparisons against immediates, registers, single-bit tests, comparisons against ranges, etc. can be realized by composing these new instructions with existing instructions.
 
 === Instruction sequences
 
@@ -61,7 +61,7 @@ More complex conditions, such as comparisons against immediates, registers, sing
 
 |*Conditional add, if zero* +
 `rd = (rc == 0) ? (rs1 + rs2) : rs1`
-|czero.nez   rd, rs2, rc
+|czero.nez  rd, rs2, rc
 add        rd, rs1, rd
 .8+.^|2 insns
 
@@ -72,58 +72,58 @@ add        rd, rs1, rd
 
 |*Conditional subtract, if zero* +
 `rd = (rc == 0) ? (rs1 - rs2) : rs1`
-|czero.nez   rd, rs2, rc
+|czero.nez  rd, rs2, rc
 sub        rd, rs1, rd
 
 |*Conditional subtract, if non-zero* +
 `rd = (rc != 0) ? (rs1 - rs2) : rs1`
-|czero.eqz    rd, rs2, rc
+|czero.eqz  rd, rs2, rc
 sub        rd, rs1, rd
 
 |*Conditional bitwise-or, if zero* +
 `rd = (rc == 0) ? (rs1 \| rs2) : rs1`
-|czero.nez   rd, rs2, rc
+|czero.nez  rd, rs2, rc
 or         rd, rs1, rd
 
 |*Conditional bitwise-or, if non-zero* +
 `rd = (rc != 0) ? (rs1 \| rs2) : rs1`
-|czero.eqz    rd, rs2, rc
+|czero.eqz  rd, rs2, rc
 or         rd, rs1, rd
 
 |*Conditional bitwise-xor, if zero* +
 `rd = (rc == 0) ? (rs1 ^ rs2) : rs1`
-|czero.nez   rd, rs2, rc
+|czero.nez  rd, rs2, rc
 xor        rd, rs1, rd
 
 |*Conditional bitwise-xor, if non-zero* +
 `rd = (rc != 0) ? (rs1 ^ rs2) : rs1`
-|czero.eqz    rd, rs2, rc
+|czero.eqz  rd, rs2, rc
 xor        rd, rs1, rd
 
 |*Conditional bitwise-and, if zero* +
 `rd = (rc == 0) ? (rs1 & rs2) : rs1`
 |and        rd, rs1, rs2
-czero.eqz    rtmp, rs1, rc
+czero.eqz  rtmp, rs1, rc
 or         rd, rd, rtmp
 .4+.^|3 insns +
 (requires 1 temporary)
 
 |*Conditional bitwise-and, if non-zero* +
 `rd = (rc != 0) ? (rs1 & rs2) : rs1`
 |and        rd, rs1, rs2
-czero.nez   rtmp, rs1, rc
+czero.nez  rtmp, rs1, rc
 or         rd, rd, rtmp
 
 |*Conditional select, if zero* +
 `rd = (rc == 0) ? rs1 : rs2`
-|czero.nez   rd, rs1, rc
-czero.eqz    rtmp, rs2, rc
+|czero.nez  rd, rs1, rc
+czero.eqz  rtmp, rs2, rc
 or         rd, rd, rtmp
 
 |*Conditional select, if non-zero* +
 `rd = (rc != 0) ? rs1 : rs2`
-|czero.eqz    rd, rs1, rc
-czero.nez   rtmp, rs2, rc
+|czero.eqz  rd, rs1, rc
+czero.nez  rtmp, rs2, rc
 or         rd, rd, rtmp
 
 |===
@@ -164,6 +164,8 @@ In effect, if the value of register _rs2_ is zero, place 0 (zero) into the regis
 These branch-based semantics do not prevent implementing this instruction as a simple select (e.g., "(rs2==0) ? 0 : rs1").
 Instead, they allow for more sophisticated implementations where a zero-result can be returned when the condition (rs2==0) is true without waiting for _rs1_ to be available.
 Furthermore, implementations can predict the condition just as they might for branches.
+
+As a consequence of this instruction's equivalence to `mv rd, rs1` when _rs2_ is nonzero, this instruction's timing is independent of the data value of _rs1_ if the Zkt extension is implemented.
 ====
 
 Operation::
@@ -188,11 +190,11 @@ Pseudocode::
 --
 
 <<<
-[#insns-czero-nez,reftext="Conditional zero, if condition is not-zero"]
+[#insns-czero-nez,reftext="Conditional zero, if condition is nonzero"]
 === czero.nez
 
 Synopsis::
-Moves zero to a register _rd_, if the condition _rs2_ is not-zero, otherwise moves _rs1_ to _rd_.
+Moves zero to a register _rd_, if the condition _rs2_ is nonzero, otherwise moves _rs1_ to _rd_.
 
 Mnemonic::
 czero.nez _rd_, _rs1_, _rs2_
@@ -221,6 +223,9 @@ In effect, if the value of register _rs2_ is non-zero, place 0 (zero) into the r
 These branch-based semantics do not prevent implementing this instruction as a simple select (e.g., "(rs2!=0) ? 0 : rs1").
 Instead, they allow for more sophisticated implementations where a zero-result can be returned when the condition (rs2!=0) is true without waiting for _rs1_ to be available.
 Furthermore, implementations can predict the condition just as they might for branches.
+However, the timing is independent of the data value in rs1.
+
+As a consequence of this instruction's equivalence to `mv rd, rs1` when _rs2_ is zero, this instruction's timing is independent of the data value of _rs1_ if the Zkt extension is implemented.
 ====
 
 Operation::