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[AArch64/ARM64] Update to Capstone v6/auto-sync #4011

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Dec 19, 2023
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[AArch64/ARM64] Update to Capstone v6/auto-sync #4011

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17 changes: 17 additions & 0 deletions librz/analysis/analysis.c
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,23 @@ RZ_LIB_VERSION(rz_analysis);

static RzAnalysisPlugin *analysis_static_plugins[] = { RZ_ANALYSIS_STATIC_PLUGINS };

/**
* \brief Returns the default size byte width of memory access operations.
* The size is just a best guess.
*
* \param analysis The current RzAnalysis in use.
*
* \return The default width of a memory access in bytes.
*/
RZ_API ut32 rz_analysis_guessed_mem_access_width(RZ_NONNULL const RzAnalysis *analysis) {
if (analysis->bits == 16 && RZ_STR_EQ(analysis->cur->arch, "arm")) {
// Thumb access is usually 4 bytes of memory by default.
return 4;
}
// Best guess for variable size.
return analysis->bits / 8;
}

RZ_API void rz_analysis_set_limits(RzAnalysis *analysis, ut64 from, ut64 to) {
free(analysis->limit);
analysis->limit = RZ_NEW0(RzAnalysisRange);
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31 changes: 20 additions & 11 deletions librz/analysis/arch/arm/arm_accessors64.h
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Expand Up @@ -9,21 +9,30 @@

#include <capstone/capstone.h>

#define IMM64(x) (ut64)(insn->detail->arm64.operands[x].imm)
#define INSOP64(x) insn->detail->arm64.operands[x]
#define IMM64(x) (ut64)(insn->detail->CS_aarch64_.operands[x].imm)
#define INSOP64(x) insn->detail->CS_aarch64_.operands[x]

#define REGID64(x) insn->detail->arm64.operands[x].reg
#define REGBASE64(x) insn->detail->arm64.operands[x].mem.base
#define REGID64(x) insn->detail->CS_aarch64_.operands[x].reg
#define REGBASE64(x) insn->detail->CS_aarch64_.operands[x].mem.base
// s/index/base|reg/
#define HASMEMINDEX64(x) (insn->detail->arm64.operands[x].mem.index != ARM64_REG_INVALID)
#define MEMDISP64(x) (ut64) insn->detail->arm64.operands[x].mem.disp
#define ISIMM64(x) (insn->detail->arm64.operands[x].type == ARM64_OP_IMM)
#define ISREG64(x) (insn->detail->arm64.operands[x].type == ARM64_OP_REG)
#define ISMEM64(x) (insn->detail->arm64.operands[x].type == ARM64_OP_MEM)
#define HASMEMINDEX64(x) (insn->detail->CS_aarch64_.operands[x].mem.index != CS_AARCH64(_REG_INVALID))
#define MEMDISP64(x) (ut64) insn->detail->CS_aarch64_.operands[x].mem.disp
#define ISIMM64(x) (insn->detail->CS_aarch64_.operands[x].type == CS_AARCH64(_OP_IMM))
#define ISREG64(x) (insn->detail->CS_aarch64_.operands[x].type == CS_AARCH64(_OP_REG))
#define ISMEM64(x) (insn->detail->CS_aarch64_.operands[x].type == CS_AARCH64(_OP_MEM))

#define LSHIFT2_64(x) insn->detail->arm64.operands[x].shift.value
#define OPCOUNT64() insn->detail->arm64.op_count
#define LSHIFT2_64(x) insn->detail->CS_aarch64_.operands[x].shift.value
#define OPCOUNT64() insn->detail->CS_aarch64_.op_count

#if CS_NEXT_VERSION < 6
#define ISWRITEBACK64() (insn->detail->arm64.writeback == true)
#else
#define ISWRITEBACK64() (insn->detail->writeback == true)
#endif
#if CS_NEXT_VERSION < 6
#define ISPREINDEX64() (((OPCOUNT64() == 2) && (ISMEM64(1)) && (ISWRITEBACK64())) || ((OPCOUNT64() == 3) && (ISMEM64(2)) && (ISWRITEBACK64())))
#define ISPOSTINDEX64() (((OPCOUNT64() == 3) && (ISIMM64(2)) && (ISWRITEBACK64())) || ((OPCOUNT64() == 4) && (ISIMM64(3)) && (ISWRITEBACK64())))
#else
#define ISPREINDEX64() (!insn->detail->CS_aarch64_.post_index && ISWRITEBACK64())
#define ISPOSTINDEX64() (insn->detail->CS_aarch64_.post_index && ISWRITEBACK64())
#endif
3 changes: 2 additions & 1 deletion librz/analysis/arch/arm/arm_cs.h
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Expand Up @@ -6,6 +6,7 @@

#include <rz_analysis.h>
#include <capstone/capstone.h>
#include "../../asm/arch/arm/aarch64_meta_macros.h"

RZ_IPI int rz_arm_cs_analysis_op_32_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, csh *handle, cs_insn *insn, bool thumb);
RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, csh *handle, cs_insn *insn);
Expand All @@ -18,7 +19,7 @@ RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, ARMCC_CondCode
#else
RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, arm_cc cond_type);
#endif
RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, arm64_cc cond_type);
RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, CS_aarch64_cc() cond_type);

RZ_IPI RzILOpEffect *rz_arm_cs_32_il(csh *handle, cs_insn *insn, bool thumb);
RZ_IPI RzAnalysisILConfig *rz_arm_cs_32_il_config(bool big_endian);
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4 changes: 4 additions & 0 deletions librz/analysis/arch/arm/arm_esil32.c
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Expand Up @@ -272,7 +272,11 @@ RZ_IPI int rz_arm_cs_analysis_op_32_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a
case ARM_INS_BKPT:
rz_strbuf_setf(&op->esil, "%d,%d,TRAP", IMM(0), IMM(0));
break;
#if CS_NEXT_VERSION < 6
case ARM_INS_NOP:
#else
case ARM_INS_HINT:
#endif
rz_strbuf_setf(&op->esil, ",");
break;
case ARM_INS_BL:
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