Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Update AGA.guide #97

Open
wants to merge 1 commit into
base: master
Choose a base branch
from
Open

Update AGA.guide #97

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
20 changes: 10 additions & 10 deletions doc/amiga/aga/AGA.guide
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
## $VER: AGA.guide 1.0 (29.Aug.93)
## Done by T.F.A. 1993
##
## Pandore ChipSet AmigaGuide� documentation.
## Pandore ChipSet AmigaGuide® documentation.
Copy link
Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

don't know why this line came in. On my mac it looks like the diff "fixes" a broken (R) char, but feel free to not include that edit.

##

##
Expand Down Expand Up @@ -317,7 +317,7 @@ PTL,PTH = 20 bit pointer that addresses DMA data. Must be reloaded by a
LCL,LCH = 20 bit location (starting address) of DMAdata. Used to
automatically restart pointers. such as the Coprocessor program counter
(during vertical blank), and the audio sample counter (whenever the
audio lentgh count is finished), (Old chips - 18 bits).
audio length count is finished), (Old chips - 18 bits).
MOD = 15 bit Modulo. A number that is automatically added to the memory
address at the end of each line to generate the address for the
beginning of the next line. This allows the blitter (or the display
Expand Down Expand Up @@ -346,7 +346,7 @@ NAME ADDR R/W CHIP(s) FUNCTION
@{"INTREQR" link INTREQ} ~01E R P Interrupt request bits read
@{"DSKPTH" link DSKPTH} + ~020 W A Disk pointer (high 5 bits)
@{"DSKPTL" link DSKPTH} + ~022 W A Disk pointer (low 15 bits)
@{"DSKLEN" link DSKLEN} ~024 W P Disk lentgh
@{"DSKLEN" link DSKLEN} ~024 W P Disk lenght
@{"DSKDAT" link DSKDAT} & ~026 W P Disk DMA data write
@{"REFPTR" link REFPTR} & ~028 W A Refresh pointer
@{"VPOSW" link VPOSR} ~02A W A Write vert most sig. bits(and frame flop)
Expand Down Expand Up @@ -419,31 +419,31 @@ NAME ADDR R/W CHIP(s) FUNCTION
@{"ADKCON" link ADKCON} 09E W P Audio,disk,UART,control
@{"AUD0LCH" link AUDxLCH} + 0A0 W A Audio channel 0 location (high 5 bits)
@{"AUD0LCL" link AUDxLCL} + 0A2 W A Audio channel 0 location (low 15 bits)
@{"AUD0LEN" link AUDxLEN} 0A4 W P Audio channel 0 lentgh
@{"AUD0LEN" link AUDxLEN} 0A4 W P Audio channel 0 length
@{"AUD0PER" link AUDxPER} 0A6 W P Audio channel 0 period
@{"AUD0VOL" link AUDxVOL} 0A8 W P Audio channel 0 volume
@{"AUD0DAT" link AUDxDAT} & 0AA W P Audio channel 0 data
0AC
0AE
@{"AUD1LCH" link AUDxLCH} + 0B0 W A Audio channel 1 location (high 5 bits)
@{"AUD1LCL" link AUDxLCL} + 0B2 W A Audio channel 1 location (low 15 bits)
@{"AUD1LEN" link AUDxLEN} 0B4 W P Audio channel 1 lentgh
@{"AUD1LEN" link AUDxLEN} 0B4 W P Audio channel 1 length
@{"AUD1PER" link AUDxPER} 0B6 W P Audio channel 1 period
@{"AUD1VOL" link AUDxVOL} 0B8 W P Audio channel 1 volume
@{"AUD1DAT" link AUDxDAT} & 0BA W P Audio channel 1 data
0BC
0BE
@{"AUD2LCH" link AUDxLCH} + 0C0 W A Audio channel 2 location (high 5 bits)
@{"AUD2LCL" link AUDxLCL} + 0C2 W A Audio channel 2 location (low 15 bits)
@{"AUD2LEN" link AUDxLEN} 0C4 W P Audio channel 2 lentgh
@{"AUD2LEN" link AUDxLEN} 0C4 W P Audio channel 2 length
@{"AUD2PER" link AUDxPER} 0C6 W P Audio channel 2 period
@{"AUD2VOL" link AUDxVOL} 0C8 W P Audio channel 2 volume
@{"AUD2DAT" link AUDxDAT} & 0CA W P Audio channel 2 data
0CC
0CE
@{"AUD3LCH" link AUDxLCH} + 0D0 W A Audio channel 3 location (high 5 bits)
@{"AUD3LCL" link AUDxLCL} + 0D2 W A Audio channel 3 location (low 15 bits)
@{"AUD3LEN" link AUDxLEN} 0D4 W P Audio channel 3 lentgh
@{"AUD3LEN" link AUDxLEN} 0D4 W P Audio channel 3 length
@{"AUD3PER" link AUDxPER} 0D6 W P Audio channel 3 period
@{"AUD3VOL" link AUDxVOL} 0D8 W P Audio channel 3 volume
@{"AUD3DAT" link AUDxDAT} & 0DA W P Audio channel 3 data
Expand Down Expand Up @@ -709,7 +709,7 @@ NAME rev ADDR type chip Description
---------------------------------------------------------------------------
AUDxLEN 0A4 W P Audio channel x length

This reg contains the lentgh (number of words) of
This reg contains the length (number of words) of
audio channel x DMA data.
@endnode
@node AUDxPER AUDxPER
Expand Down Expand Up @@ -757,7 +757,7 @@ AUDxDAT 0AA W P Audio channel x data
channel controller automatically transfers data
to this reg from RAM. The processor can also
write directly to this reg. When the DMA data is
finished (words outputted=lentgh)and the data in
finished (words outputted=length)and the data in
this reg has been used, an audio channel interrupt
request is set.
@endnode
Expand Down Expand Up @@ -835,7 +835,7 @@ DUAL = Run the horizontal comparators with the alternate horizontal beam
pointers to come out more than once in a horizontal line,
assuming there is some memory bandwidth left (it doesn`t work in
640*400*4 interlace mode) also, to keep the two displays synced,
the horizontal line lentghs should be multiples of each other.
the horizontal line lengths should be multiples of each other.
If you are amazingly clever, you might not need to do this.

PAL = Set appropriate decodes (in normal mode) for PAL. In variable
Expand Down