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Linking 7Sig to HPS2FPGA on Arria 10
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robseb committed Apr 11, 2021
1 parent adfedd1 commit 333378d
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Showing 3 changed files with 16 additions and 7 deletions.
8 changes: 4 additions & 4 deletions examples/python/SevenSigCounter.py
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@
if __name__ == '__main__':
print('Counting a number on the Seven Segment Display with a Linux shell command!\n')

# Check that the running board is a Terasic DE10-Standard- or Han Pilot Development Board
# Check that the running board is a Terasic DE10-Standard- or Terasic Han Pilot Development Board
# Used development board
devboard = 1 # 0: DE10 Standard | 1: DE10 Nano | 2: Han Pilot

Expand All @@ -42,9 +42,9 @@
# Count the Seven Segment Display with a rstools shell command
for count in range(SEVENSIG_MAX_VALUE[devboard]):
print('Sample: '+str(count)+'/'+str(SEVENSIG_MAX_VALUE[devboard]))

if(devboard==2):
os.system('FPGA-writeBridge -lw 8 -h '+ str(count) +' -b')
if(devboard==2): # HAN Pilot Board
os.system('FPGA-writeBridge -hf 8 -h '+ str(count) +' -b')
else: # DE10 Standard Board
os.system('FPGA-writeBridge -lw 38 -h '+ str(count) +' -b')

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15 changes: 12 additions & 3 deletions examples/python/fpgaSevenSigCounterMemory.py
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Expand Up @@ -23,13 +23,21 @@
from time import sleep


# the HPS Lightweight HPS-to-FPGA bridge address offset
# The HPS Lightweight HPS-to-FPGA bridge address offset (Cyclone V and Arria 10)
HPS_LW_ADRS_OFFSET = 0xFF200000

# The HPS HPS-to-FPGA bridge address offset (Cyclone V and Arria 10)
HPS_ADRS_OFFSET = 0xC0000000

# The offset address of the seven segment Display Controller
# DE10 Standard, , HAN Pilot
SEVENSIG_ADDRES_OFFSET = [0x038,0x0,0x008]

# The used bridge interface offset address for the baord
# DE10 Standard, , HAN Pilot
SEVENSIG_BRIDGE_ADDRES_OFFSET = [HPS_LW_ADRS_OFFSET,0x0,HPS_ADRS_OFFSET]


ledValue = 0

# Selected maximum countable value for the SevenSig Display
Expand All @@ -55,12 +63,13 @@
devboard = 2

if devboard==1:
print("Error: This script only works with a Terasic DE10 Standard- or Han Pilot Board!")
print("Error: This script only works with a Terasic DE10 Standard- or Terasic HAN Pilot Board!")
sys.exit()

# Open the memory access to the Lightweight HPS-to-FPGA bridge
# (Base address, byte len to accesses, interface)
de = devmem.DevMem(HPS_LW_ADRS_OFFSET, SEVENSIG_ADDRES_OFFSET[devboard]+1, "/dev/mem")
de = devmem.DevMem(SEVENSIG_BRIDGE_ADDRES_OFFSET[devboard], \
SEVENSIG_ADDRES_OFFSET[devboard]+1, "/dev/mem")

for var in range(SEVENSIG_MAX_VALUE[devboard]):
print('Sample: '+str(var)+'/'+str(SEVENSIG_MAX_VALUE[devboard]))
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Binary file added fpga/HANrsyocto.qar
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