foss-for-fpga: added sv2v and performed a few tweaks

Closes #22

slides/foss-for-fpga.md

@@ -344,6 +344,18 @@ Using formal mathematic methods (assumptions and assertions) for proving the cor
 * **openFPGALoader:** universal utility for programming FPGA
 * **dfu-util:** **D**evice **F**irmware **U**pgrade **Uti**lities (USB)
 
+---
+
+### System Verilog Support
+
+* UHDM: Universal Hardware Data Model
+* Surelog: SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler (work in progress to integrate with Yosys and Verilator)
+* Verible: SystemVerilog 2017 parser for developer tools (linter, formatter, indexer, lexical diff, others)
+
+![Chips Alliance](images/logos/chips-alliance.png)    ![Antmicro](images/logos/antmicro.png)
+
+* sv2v: SystemVerilog to Verilog conversion (emphasis on supporting synthesizable language constructs)
+
 ---
 <!-- ###################################################################### -->
 ## Development
@@ -354,7 +366,7 @@ Using formal mathematic methods (assumptions and assertions) for proving the cor
 
 ---
 
-### Project Managers
+### Building systems
 
 * **edalize:** a Python Library for interacting with EDA tools (was part of FuseSoC, now its build backend).
 * **HDLmake:** tool for generating multi-purpose Makefiles for FPGA projects (CERN)
@@ -370,6 +382,14 @@ Using formal mathematic methods (assumptions and assertions) for proving the cor
 
 ---
 
+### TerosHDL (VScode plugin)
+
+![TerosHDL](images/screens/teroshdl.png)
+
+Suports GHDL, Yosys, VUnit, GTKwave, Verilator, cocotb, edalize, icestorm, Trellis, Symbiflow...
+
+---
+
 ### Libraries, Collections, IP Cores
 
 * **PoC (Pile of Cores Library):** a library of free, open-source and platform independent IP cores.
@@ -400,24 +420,6 @@ Using formal mathematic methods (assumptions and assertions) for proving the cor
 
 ![RISC-V](images/diagrams/risc-v.png)
 
----
-
-### TerosHDL (VScode plugin)
-
-![TerosHDL](images/screens/teroshdl.png)
-
-Suports GHDL, Yosys, VUnit, GTKwave, Verilator, cocotb, edalize, icestorm, Trellis, Symbiflow...
-
----
-
-### System Verilog Support
-
-* UHDM: Universal Hardware Data Model
-* Surelog: SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler (work in progress to integrate with Yosys and Verilator)
-* Verible: SystemVerilog 2017 parser for developer tools (linter, formatter, indexer, lexical diff, others)
-
-![Chips Alliance](images/logos/chips-alliance.png)&nbsp;&nbsp;&nbsp;&nbsp;![Antmicro](images/logos/antmicro.png)
-
 ---
 <!-- ###################################################################### -->
 ## Hardware