Support R_RISCV_SET_ULEB128 and R_RISCV_SUB_ULEB128

riscv-non-isa/riscv-elf-psabi-doc#361
rui314 · Mar 31, 2023 · 4bffe26 · 4bffe26
1 parent 290b4ea
commit 4bffe26
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diff --git a/elf/arch-riscv.cc b/elf/arch-riscv.cc
@@ -149,6 +149,13 @@ static void write_cjtype(u8 *loc, u32 val) {
   *(ul16 *)loc |= cjtype(val);
 }
 
+static void overwrite_uleb(u8 *loc, u64 val) {
+  while (*loc & 0b1000'0000) {
+    *loc++ = 0b1000'0000 | (val & 0b0111'1111);
+    val >>= 7;
+  }
+}
+
 // Returns the rd register of an R/I/U/J-type instruction.
 static u32 get_rd(u32 val) {
   return bits(val, 11, 7);
@@ -621,6 +628,15 @@ void InputSection<E>::apply_reloc_nonalloc(Context<E> &ctx, u8 *base) {
     case R_RISCV_SET32:
       *(U32<E> *)loc = S + A;
       break;
+    case R_RISCV_SET_ULEB128:
+      overwrite_uleb(loc, S + A);
+      break;
+    case R_RISCV_SUB_ULEB128: {
+      u8 *p = loc;
+      u64 val = read_uleb(p);
+      overwrite_uleb(loc, val - S - A);
+      break;
+    }
     default:
       Fatal(ctx) << *this << ": invalid relocation for non-allocated sections: "
                  << rel;

diff --git a/elf/elf.cc b/elf/elf.cc
@@ -404,6 +404,8 @@ std::string rel_to_string<RV64LE>(u32 r_type) {
   case R_RISCV_32_PCREL: return "R_RISCV_32_PCREL";
   case R_RISCV_IRELATIVE: return "R_RISCV_IRELATIVE";
   case R_RISCV_PLT32: return "R_RISCV_PLT32";
+  case R_RISCV_SET_ULEB128: return "R_RISCV_SET_ULEB128";
+  case R_RISCV_SUB_ULEB128: return "R_RISCV_SUB_ULEB128";
   }
   return "unknown (" + std::to_string(r_type) + ")";
 }

diff --git a/elf/elf.h b/elf/elf.h
@@ -757,6 +757,8 @@ enum : u32 {
   R_RISCV_32_PCREL = 57,
   R_RISCV_IRELATIVE = 58,
   R_RISCV_PLT32 = 59,
+  R_RISCV_SET_ULEB128 = 60,
+  R_RISCV_SUB_ULEB128 = 61,
 };
 
 enum : u32 {