Support user thread mode in hard fault handler

[crawford]

No description provided.

[japaric]

Thanks for the PR, @crawford. I more or less understand what the assembly routine is doing but could you add a comment indicating with text (or the equivalent Rust code) what the instructions are doing and another comment mentioning the difference between the MSP and the PSP (a link to ARM docs is fine)?

bors try

^ to check if this works on ARMv6-M

[bors]

try

Build failed

• continuous-integration/travis-ci/push

[crawford]

Sorry, I've been busy at work. I'll fix up this PR.

[crawford]

bors try

EDIT: It was worth a shot.

[bors]

🔒 Permission denied

Existing reviewers: click here to make crawford a reviewer

[crawford]

I switched to a slower implementation that will work on ARM v6 and v7. We could use two different implementations, but I don't think it's worth the complexity.

[japaric]

Shouldn't this say "bit[2]"? Bit positions start at 0 to have bitmasks match 1 << $pos (bit 0 -> mask = (1 << 0); bit 1 -> mask = (1 << 1); etc.)

---

I think you can use bmi instead of tst to use less registers. For example, this code

#![no_std]
#![feature(asm)]
#![feature(core_intrinsics)]

use core::intrinsics;

pub fn foo(x: u32) {
    unsafe {
        if x & (1 << 2) == 0 {
            asm!("mrs r0, MSP
                  bl UserHardFault" :::: "volatile");
            intrinsics::unreachable();
        } else {
            asm!("mrs r0, PSP
                  bl UserHardFault" :::: "volatile");
            intrinsics::unreachable();
        }
    }
}

produces this machine code when compiled with optimizations:

00000000 <foo::foo>:
   0:   0740            lsls    r0, r0, #29
   2:   d404            bmi.n   e <foo::foo+0xe>
   4:   f3ef 8008       mrs     r0, MSP
   8:   f7ff fffe       bl      0 <UserHardFault>
   c:   defe            udf     #254    ; 0xfe
   e:   f3ef 8009       mrs     r0, PSP
  12:   f7ff fffe       bl      0 <UserHardFault>
  16:   defe            udf     #254    ; 0xfe

The defe udf instruction can be omitted.

[japaric]

bors try

[bors]

try

Build failed

• continuous-integration/travis-ci/push

[crawford]

Updated. I haven't tested this implementation on real hardware though. I'll be able to test it tomorrow.

[crawford]

This looks good on the Cortex M4 I tested. While attempting to write to address 0x3000_0000, I hit a hardfault:

(gdb) print/x *frame
$3 = cortex_m_rt::ExceptionFrame {r0: 0x30000000, r1: 0x0, r2: 0x0, r3: 0xec, r12: 0xec, lr: 0x24073, pc: 0x11882, xpsr: 0x41000000}

[japaric]

It appears this still doesn't compile for ARMv6-M when using clang:

running: "clang" "-O0" "-ffunction-sections" "-fdata-sections" "-fPIC" "-g" "--target=thumbv6m-none-eabi" "-Wall" "-Wextra" "-o" "/home/japaric/rust/cortex-m-rt/target/thumbv6m-none-eabi/debug/build/cortex-m-rt-2722f9a967a9ffc0/out/hardfault.o" "-c" "hardfault.s"
cargo:warning=clang-6.0: warning: argument unused during compilation: '-ffunction-sections' [-Wunused-command-line-argument]
cargo:warning=clang-6.0: warning: argument unused during compilation: '-fdata-sections' [-Wunused-command-line-argument]
cargo:warning=hardfault.s:4:3: error: invalid instruction, any one of the following would fix this:
cargo:warning=  movs r0, lr
cargo:warning=  ^
cargo:warning=hardfault.s:4:12: note: operand must be an immediate in the range [0,255]
cargo:warning=  movs r0, lr
cargo:warning=           ^
cargo:warning=hardfault.s:4:12: note: operand must be a register in range [r0, r7]
cargo:warning=  movs r0, lr
cargo:warning=           ^
cargo:warning=hardfault.s:5:3: error: invalid instruction, any one of the following would fix this:
cargo:warning=  lsl  r0, r0, #29     // Test bit[2] of EXC_RETURN to determine thread mode
cargo:warning=  ^
cargo:warning=hardfault.s:5:3: note: instruction requires: thumb2
cargo:warning=  lsl  r0, r0, #29     // Test bit[2] of EXC_RETURN to determine thread mode
cargo:warning=  ^
cargo:warning=hardfault.s:5:3: note: no flag-preserving variant of this instruction available
cargo:warning=  lsl  r0, r0, #29     // Test bit[2] of EXC_RETURN to determine thread mode
cargo:warning=  ^
cargo:warning=hardfault.s:5:16: note: operand must be a register in range [r0, r7]
cargo:warning=  lsl  r0, r0, #29     // Test bit[2] of EXC_RETURN to determine thread mode
cargo:warning=               ^
exit code: 1

bors try

[japaric]

bors r+

[bors]

Build failed

• continuous-integration/travis-ci/push

[crawford]

Shoot. I hadn't noticed the individual failures were different. I'm on vacation at the moment, but I can fix this in a couple days.

[japaric]

Hello @crawford! We haven't heard from you in a while so I'm going to close this PR to clear up the PR queue.

Feel free to open a new rebased PR and we'll be happy to review it!

[crawford]

No problem. Sorry I went AWOL.