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Penultimate wasm SIMD update (hopefully) #101

Merged
merged 7 commits into from
Apr 27, 2021
Merged

Penultimate wasm SIMD update (hopefully) #101

merged 7 commits into from
Apr 27, 2021

Commits on Apr 19, 2021

  1. [WebAssembly] Add shuffles as an option for lowering BUILD_VECTOR 

    When lowering a BUILD_VECTOR SDNode, we choose among various possible vector
creation instructions in an attempt to minimize the total number of instructions
used. We previously considered using swizzles, consts, and splats, and this
patch adds shuffles as well. A common pattern that now lowers to shuffles is
when two 64-bit vectors are concatenated. Previously, concatenations generally
lowered to sequences of extract_lane and replace_lane instructions when they
could have been a single shuffle.

Differential Revision: https://reviews.llvm.org/D100018
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    tlively authored and alexcrichton committed Apr 19, 2021
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  2. [WebAssembly] Update v128.any_true 

    In the final SIMD spec, there is only a single v128.any_true instruction, rather
than one for each lane interpretation because the semantics do not depend on the
lane interpretation.

Differential Revision: https://reviews.llvm.org/D100241
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  3. [WebAssembly] Test i64x2.abs encoding 

    This test was disabled despite the instruction having been implemented for a
long time. This commit just enables the test.

Differential Revision: https://reviews.llvm.org/D100345
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  4. [WebAssembly] Use standard intrinsics for f32x4 and f64x2 ops 

    Now that these instructions are no longer prototypes, we do not need to be
careful about keeping them opt-in and can use the standard LLVM infrastructure
for them. This commit removes the bespoke intrinsics we were using to represent
these operations in favor of the corresponding target-independent intrinsics.
The clang builtins are preserved because there is no standard way to easily
represent these operations in C/C++.

For consistency with the scalar codegen in the Wasm backend, the intrinsic used
to represent {f32x4,f64x2}.nearest is @llvm.nearbyint even though
@llvm.roundeven better captures the semantics of the underlying Wasm
instruction. Replacing our use of @llvm.nearbyint with use of @llvm.roundeven is
left to a potential future patch.

Differential Revision: https://reviews.llvm.org/D100411
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  5. [WebAssembly] Codegen for f64x2.convert_low_i32x4_{s,u} 

    Add a custom DAG combine and ISD opcode for detecting patterns like

  (uint_to_fp (extract_subvector ...))

before the extract_subvector is expanded to ensure that they will ultimately
lower to f64x2.convert_low_i32x4_{s,u} instructions. Since these instructions
are no longer prototypes and can now be produced via standard IR, this commit
also removes the target intrinsics and builtins that had been used to prototype
the instructions.

Differential Revision: https://reviews.llvm.org/D100425
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  6. [WebAssembly] Codegen for i64x2.extend_{low,high}_i32x4_{s,u} 

    Removes the builtins and intrinsics used to opt in to using these instructions
and replaces them with normal ISel patterns now that they are no longer
prototypes.

Differential Revision: https://reviews.llvm.org/D100402
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  7. [WebAssembly] Remove saturating fp-to-int target intrinsics 

    Use the target-independent @llvm.fptosi and @llvm.fptoui intrinsics instead.
This includes removing the instrinsics for i32x4.trunc_sat_zero_f64x2_{s,u},
which are now represented in IR as a saturating truncation to a v2i32 followed by
a concatenation with a zero vector.

Differential Revision: https://reviews.llvm.org/D100596
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