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Cherry-pick [RISCV] Initial support .insn directive for the assembler. #121

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merged 1 commit into from
Dec 4, 2021

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piegamesde
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This allows for a custom encoding to be emitted. It can also be
used with inline assembly to allow the custom instruction to be
register allocated like other instructions.

I initially started from SystemZ's implementation, but some of
the formats allow operands to be specified in multiple ways so I
had to add support for matching different operand class lists for
the same format. That implementation is a simplified version of
what is emitted by tablegen for regular instructions.

I've left out the compressed formats. And I haven't supported the
named opcodes like LUI or OP_IMM_32. Those can be added in future
patches.

Documentation can be found here https://sourceware.org/binutils/docs-2.37/as/RISC_002dV_002dFormats.html

Reviewed By: jrtc27, MaskRay

Differential Revision: https://reviews.llvm.org/D108602
@cuviper
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cuviper commented Dec 4, 2021

Looks good to me.

@cuviper cuviper merged commit 2b9078f into rust-lang:rustc/13.0-2021-09-30 Dec 4, 2021
matthiaskrgr added a commit to matthiaskrgr/rust that referenced this pull request Dec 4, 2021
vext01 pushed a commit to vext01/llvm-project that referenced this pull request Mar 21, 2024
Revert Stackmap change from PR#119
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3 participants