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Auto merge of #58406 - Disasm:rv64-support, r=nagisa
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Add riscv64{imac,gc}-unknown-none-elf targets

Previous attempt by @fintelia: #58012

Related: rust-embedded/wg#218
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@bors
bors committed Feb 15, 2019
2 parents f058741 + 1f1a824 commit a9410cd
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Showing 6 changed files with 69 additions and 1 deletion.
2 changes: 2 additions & 0 deletions src/ci/docker/dist-various-1/Dockerfile
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Expand Up @@ -112,6 +112,8 @@ ENV TARGETS=$TARGETS,thumbv7em-none-eabihf
ENV TARGETS=$TARGETS,thumbv8m.main-none-eabi
ENV TARGETS=$TARGETS,riscv32imc-unknown-none-elf
ENV TARGETS=$TARGETS,riscv32imac-unknown-none-elf
ENV TARGETS=$TARGETS,riscv64imac-unknown-none-elf
ENV TARGETS=$TARGETS,riscv64gc-unknown-none-elf
ENV TARGETS=$TARGETS,armebv7r-none-eabi
ENV TARGETS=$TARGETS,armebv7r-none-eabihf
ENV TARGETS=$TARGETS,armv7r-none-eabi
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2 changes: 2 additions & 0 deletions src/librustc_target/spec/mod.rs
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Expand Up @@ -451,6 +451,8 @@ supported_targets! {

("riscv32imc-unknown-none-elf", riscv32imc_unknown_none_elf),
("riscv32imac-unknown-none-elf", riscv32imac_unknown_none_elf),
("riscv64imac-unknown-none-elf", riscv64imac_unknown_none_elf),
("riscv64gc-unknown-none-elf", riscv64gc_unknown_none_elf),

("aarch64-unknown-none", aarch64_unknown_none),

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31 changes: 31 additions & 0 deletions src/librustc_target/spec/riscv64gc_unknown_none_elf.rs
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@@ -0,0 +1,31 @@
use crate::spec::{LinkerFlavor, LldFlavor, PanicStrategy,
Target, TargetOptions, TargetResult};

pub fn target() -> TargetResult {
Ok(Target {
data_layout: "e-m:e-p:64:64-i64:64-i128:128-n64-S128".to_string(),
llvm_target: "riscv64".to_string(),
target_endian: "little".to_string(),
target_pointer_width: "64".to_string(),
target_c_int_width: "32".to_string(),
target_os: "none".to_string(),
target_env: String::new(),
target_vendor: "unknown".to_string(),
arch: "riscv64".to_string(),
linker_flavor: LinkerFlavor::Lld(LldFlavor::Ld),

options: TargetOptions {
linker: Some("rust-lld".to_string()),
cpu: "generic-rv64".to_string(),
max_atomic_width: Some(64),
atomic_cas: true,
features: "+m,+a,+f,+d,+c".to_string(),
executables: true,
panic_strategy: PanicStrategy::Abort,
relocation_model: "static".to_string(),
emit_debug_gdb_scripts: false,
abi_blacklist: super::riscv_base::abi_blacklist(),
.. Default::default()
},
})
}
31 changes: 31 additions & 0 deletions src/librustc_target/spec/riscv64imac_unknown_none_elf.rs
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@@ -0,0 +1,31 @@
use crate::spec::{LinkerFlavor, LldFlavor, PanicStrategy,
Target, TargetOptions, TargetResult};

pub fn target() -> TargetResult {
Ok(Target {
data_layout: "e-m:e-p:64:64-i64:64-i128:128-n64-S128".to_string(),
llvm_target: "riscv64".to_string(),
target_endian: "little".to_string(),
target_pointer_width: "64".to_string(),
target_c_int_width: "32".to_string(),
target_os: "none".to_string(),
target_env: String::new(),
target_vendor: "unknown".to_string(),
arch: "riscv64".to_string(),
linker_flavor: LinkerFlavor::Lld(LldFlavor::Ld),

options: TargetOptions {
linker: Some("rust-lld".to_string()),
cpu: "generic-rv64".to_string(),
max_atomic_width: Some(64),
atomic_cas: true,
features: "+m,+a,+c".to_string(),
executables: true,
panic_strategy: PanicStrategy::Abort,
relocation_model: "static".to_string(),
emit_debug_gdb_scripts: false,
abi_blacklist: super::riscv_base::abi_blacklist(),
.. Default::default()
},
})
}
2 changes: 1 addition & 1 deletion src/llvm-project
Submodule llvm-project updated 35 files
+25 −0 llvm/include/llvm/IR/IntrinsicsRISCV.td
+67 −14 llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+295 −85 llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+25 −1 llvm/lib/Target/RISCV/RISCVISelLowering.h
+56 −77 llvm/lib/Target/RISCV/RISCVInstrInfo.td
+78 −2 llvm/lib/Target/RISCV/RISCVInstrInfoA.td
+23 −0 llvm/lib/Target/RISCV/RISCVInstrInfoD.td
+48 −0 llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+21 −18 llvm/lib/Target/RISCV/RISCVInstrInfoM.td
+712 −0 llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
+182 −0 llvm/test/CodeGen/RISCV/atomic-load-store.ll
+3,017 −0 llvm/test/CodeGen/RISCV/atomic-rmw.ll
+202 −22 llvm/test/CodeGen/RISCV/double-arith.ll
+143 −0 llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
+278 −0 llvm/test/CodeGen/RISCV/double-br-fcmp.ll
+180 −0 llvm/test/CodeGen/RISCV/double-convert.ll
+134 −0 llvm/test/CodeGen/RISCV/double-fcmp.ll
+27 −0 llvm/test/CodeGen/RISCV/double-imm.ll
+220 −9 llvm/test/CodeGen/RISCV/double-intrinsics.ll
+83 −0 llvm/test/CodeGen/RISCV/double-mem.ll
+215 −0 llvm/test/CodeGen/RISCV/double-select-fcmp.ll
+24 −0 llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
+195 −25 llvm/test/CodeGen/RISCV/float-arith.ll
+126 −0 llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll
+310 −0 llvm/test/CodeGen/RISCV/float-br-fcmp.ll
+122 −0 llvm/test/CodeGen/RISCV/float-convert.ll
+134 −0 llvm/test/CodeGen/RISCV/float-fcmp.ll
+21 −0 llvm/test/CodeGen/RISCV/float-imm.ll
+76 −0 llvm/test/CodeGen/RISCV/float-mem.ll
+215 −0 llvm/test/CodeGen/RISCV/float-select-fcmp.ll
+20 −0 llvm/test/CodeGen/RISCV/pr40333.ll
+86 −0 llvm/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll
+130 −0 llvm/test/CodeGen/RISCV/rv64d-double-convert.ll
+187 −0 llvm/test/CodeGen/RISCV/rv64f-float-convert.ll
+16 −16 llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
2 changes: 2 additions & 0 deletions src/tools/build-manifest/src/main.rs
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Expand Up @@ -85,6 +85,8 @@ static TARGETS: &'static [&'static str] = &[
"powerpc64le-unknown-linux-gnu",
"riscv32imc-unknown-none-elf",
"riscv32imac-unknown-none-elf",
"riscv64imac-unknown-none-elf",
"riscv64gc-unknown-none-elf",
"s390x-unknown-linux-gnu",
"sparc64-unknown-linux-gnu",
"sparcv9-sun-solaris",
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