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add specs for riscv32/riscv64 musl targets
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Signed-off-by: Khem Raj <raj.khem@gmail.com>
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kraj committed Feb 17, 2021
1 parent a143517 commit f049e27
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Showing 3 changed files with 40 additions and 0 deletions.
2 changes: 2 additions & 0 deletions compiler/rustc_target/src/spec/mod.rs
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Expand Up @@ -783,9 +783,11 @@ supported_targets! {
("riscv32imc-unknown-none-elf", riscv32imc_unknown_none_elf),
("riscv32imac-unknown-none-elf", riscv32imac_unknown_none_elf),
("riscv32gc-unknown-linux-gnu", riscv32gc_unknown_linux_gnu),
("riscv32gc-unknown-linux-musl", riscv32gc_unknown_linux_musl),
("riscv64imac-unknown-none-elf", riscv64imac_unknown_none_elf),
("riscv64gc-unknown-none-elf", riscv64gc_unknown_none_elf),
("riscv64gc-unknown-linux-gnu", riscv64gc_unknown_linux_gnu),
("riscv64gc-unknown-linux-musl", riscv64gc_unknown_linux_musl),

("aarch64-unknown-none", aarch64_unknown_none),
("aarch64-unknown-none-softfloat", aarch64_unknown_none_softfloat),
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19 changes: 19 additions & 0 deletions compiler/rustc_target/src/spec/riscv32gc_unknown_linux_musl.rs
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@@ -0,0 +1,19 @@
use crate::spec::{CodeModel, Target, TargetOptions};

pub fn target() -> Target {
Target {
llvm_target: "riscv32-unknown-linux-musl".to_string(),
pointer_width: 32,
data_layout: "e-m:e-p:32:32-i64:64-n32-S128".to_string(),
arch: "riscv32".to_string(),
options: TargetOptions {
unsupported_abis: super::riscv_base::unsupported_abis(),
code_model: Some(CodeModel::Medium),
cpu: "generic-rv32".to_string(),
features: "+m,+a,+f,+d,+c".to_string(),
llvm_abiname: "ilp32d".to_string(),
max_atomic_width: Some(32),
..super::linux_musl_base::opts()
},
}
}
19 changes: 19 additions & 0 deletions compiler/rustc_target/src/spec/riscv64gc_unknown_linux_musl.rs
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@@ -0,0 +1,19 @@
use crate::spec::{CodeModel, Target, TargetOptions};

pub fn target() -> Target {
Target {
llvm_target: "riscv64-unknown-linux-musl".to_string(),
pointer_width: 64,
data_layout: "e-m:e-p:64:64-i64:64-i128:128-n64-S128".to_string(),
arch: "riscv64".to_string(),
options: TargetOptions {
unsupported_abis: super::riscv_base::unsupported_abis(),
code_model: Some(CodeModel::Medium),
cpu: "generic-rv64".to_string(),
features: "+m,+a,+f,+d,+c".to_string(),
llvm_abiname: "lp64d".to_string(),
max_atomic_width: Some(64),
..super::linux_musl_base::opts()
},
}
}

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