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Fix: Change to 'rustc_legacy_const_generics'
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@coastalwhite
coastalwhite committed Aug 22, 2023
1 parent 90e5d8e commit 32542b7
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Showing 3 changed files with 120 additions and 184 deletions.
125 changes: 43 additions & 82 deletions crates/core_arch/src/riscv32/zk.rs
View file
Original file line number Diff line number Diff line change
@@ -1,19 +1,28 @@
#[allow(unused)]
use core::arch::asm;

#[allow(unused)]
macro_rules! constify_imm2 {
($imm2:expr, $expand:ident) => {
#[allow(overflowing_literals)]
match $imm2 & 0b11 {
0b00 => $expand!(0),
0b01 => $expand!(1),
0b10 => $expand!(2),
_ => $expand!(3),
}
macro_rules! static_assert_imm2 {
($imm:ident) => {
static_assert!(
$imm < 4,
"Immediate value allowed to be a constant from 0 up to including 3"
)
};
}

extern "unadjusted" {
#[link_name = "llvm.riscv.aes32esi"]
fn _aes32esi(rs1: i32, rs2: i32, bs: i32) -> i32;

#[link_name = "llvm.riscv.aes32esmi"]
fn _aes32esmi(rs1: i32, rs2: i32, bs: i32) -> i32;

#[link_name = "llvm.riscv.aes32dsi"]
fn _aes32dsi(rs1: i32, rs2: i32, bs: i32) -> i32;

#[link_name = "llvm.riscv.aes32dsmi"]
fn _aes32dsmi(rs1: i32, rs2: i32, bs: i32) -> i32;
}

/// AES final round encryption instruction for RV32.
///
/// This instruction sources a single byte from rs2 according to bs. To this it applies the
Expand All @@ -29,32 +38,20 @@ macro_rules! constify_imm2 {
///
/// # Note
///
/// The `bs` parameter is expected to be a constant value and only the bottom 2 bits of `bs` are
/// The `BS` parameter is expected to be a constant value and only the bottom 2 bits of `bs` are
/// used.
///
/// # Safety
///
/// This function is safe to use if the `zkne` target feature is present.
#[target_feature(enable = "zkne")]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(test, assert_instr(aes32esi))]
#[inline]
pub unsafe fn aes32esi(rs1: u32, rs2: u32, bs: u8) -> u32 {
macro_rules! aes32esi {
($imm2:expr) => {{
let value: u32;
unsafe {
asm!(
concat!("aes32esi {rd},{rs1},{rs2},", $imm2),
rd = lateout(reg) value,
rs1 = in(reg) rs1,
rs2 = in(reg) rs2,
options(pure, nomem, nostack),
);
}
value
}}
}
constify_imm2!(bs, aes32esi)
pub unsafe fn aes32esi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
static_assert_imm2!(BS);

_aes32esi(rs1 as i32, rs2 as i32, BS as i32) as u32
}

/// AES middle round encryption instruction for RV32 with.
Expand All @@ -79,25 +76,13 @@ pub unsafe fn aes32esi(rs1: u32, rs2: u32, bs: u8) -> u32 {
///
/// This function is safe to use if the `zkne` target feature is present.
#[target_feature(enable = "zkne")]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(test, assert_instr(aes32esmi))]
#[inline]
pub unsafe fn aes32esmi(rs1: u32, rs2: u32, bs: u8) -> u32 {
macro_rules! aes32esmi {
($imm2:expr) => {{
let value: u32;
unsafe {
asm!(
concat!("aes32esmi {rd},{rs1},{rs2},", $imm2),
rd = lateout(reg) value,
rs1 = in(reg) rs1,
rs2 = in(reg) rs2,
options(pure, nomem, nostack),
);
}
value
}}
}
constify_imm2!(bs, aes32esmi)
pub unsafe fn aes32esmi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
static_assert_imm2!(BS);

_aes32esmi(rs1 as i32, rs2 as i32, BS as i32) as u32
}

/// AES final round decryption instruction for RV32.
Expand All @@ -114,32 +99,20 @@ pub unsafe fn aes32esmi(rs1: u32, rs2: u32, bs: u8) -> u32 {
///
/// # Note
///
/// The `bs` parameter is expected to be a constant value and only the bottom 2 bits of `bs` are
/// The `BS` parameter is expected to be a constant value and only the bottom 2 bits of `bs` are
/// used.
///
/// # Safety
///
/// This function is safe to use if the `zknd` target feature is present.
#[target_feature(enable = "zknd")]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(test, assert_instr(aes32dsi))]
#[inline]
pub unsafe fn aes32dsi(rs1: u32, rs2: u32, bs: u8) -> u32 {
macro_rules! aes32dsi {
($imm2:expr) => {{
let value: u32;
unsafe {
asm!(
concat!("aes32dsi {rd},{rs1},{rs2},", $imm2),
rd = lateout(reg) value,
rs1 = in(reg) rs1,
rs2 = in(reg) rs2,
options(pure, nomem, nostack),
);
}
value
}}
}
constify_imm2!(bs, aes32dsi)
pub unsafe fn aes32dsi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
static_assert_imm2!(BS);

_aes32dsi(rs1 as i32, rs2 as i32, BS as i32) as u32
}

/// AES middle round decryption instruction for RV32.
Expand All @@ -157,32 +130,20 @@ pub unsafe fn aes32dsi(rs1: u32, rs2: u32, bs: u8) -> u32 {
///
/// # Note
///
/// The `bs` parameter is expected to be a constant value and only the bottom 2 bits of `bs` are
/// The `BS` parameter is expected to be a constant value and only the bottom 2 bits of `bs` are
/// used.
///
/// # Safety
///
/// This function is safe to use if the `zknd` target feature is present.
#[target_feature(enable = "zknd")]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(test, assert_instr(aes32dsmi))]
#[inline]
pub unsafe fn aes32dsmi(rs1: u32, rs2: u32, bs: u8) -> u32 {
macro_rules! aes32dsmi {
($imm2:expr) => {{
let value: u32;
unsafe {
asm!(
concat!("aes32dsmi {rd},{rs1},{rs2},", $imm2),
rd = lateout(reg) value,
rs1 = in(reg) rs1,
rs2 = in(reg) rs2,
options(pure, nomem, nostack),
);
}
value
}}
}
constify_imm2!(bs, aes32dsmi)
pub unsafe fn aes32dsmi<const BS: u8>(rs1: u32, rs2: u32) -> u32 {
static_assert_imm2!(BS);

_aes32dsmi(rs1 as i32, rs2 as i32, BS as i32) as u32
}

/// Place upper/lower halves of the source register into odd/even bits of the destination
Expand Down
52 changes: 17 additions & 35 deletions crates/core_arch/src/riscv64/zk.rs
View file
Original file line number Diff line number Diff line change
@@ -1,25 +1,19 @@
#[allow(unused)]
use core::arch::asm;

#[allow(unused)]
macro_rules! constify_imm_0_until_10 {
($imm2:expr, $expand:ident) => {
match $imm2 {
1 => $expand!(1),
2 => $expand!(2),
3 => $expand!(3),
4 => $expand!(4),
5 => $expand!(5),
6 => $expand!(6),
7 => $expand!(7),
8 => $expand!(8),
9 => $expand!(9),
10 => $expand!(10),
_ => $expand!(0),
}
macro_rules! static_assert_imm_0_until_10 {
($imm:ident) => {
static_assert!(
$imm <= 10,
"Immediate value allowed to be a constant from 0 up to including 10"
)
};
}

extern "unadjusted" {
#[link_name = "llvm.riscv.aes64ks1i"]
fn _aes64ks1i(rs1: i64, rnum: i32) -> i64;
}

/// AES final round encryption instruction for RV64.
///
/// Uses the two 64-bit source registers to represent the entire AES state, and produces half
Expand Down Expand Up @@ -168,31 +162,19 @@ pub unsafe fn aes64dsm(rs1: u64, rs2: u64) -> u64 {
///
/// # Note
///
/// The `rnum` parameter is expected to be a constant value inside the range of `0..=10`, if a
/// value outside the valid range is given it uses `rnum=0`.
/// The `RNUM` parameter is expected to be a constant value inside the range of `0..=10`.
///
/// # Safety
///
/// This function is safe to use if the `zkne` or `zknd` target feature is present.
#[target_feature(enable = "zkne", enable = "zknd")]
#[rustc_legacy_const_generics(1)]
#[cfg_attr(test, assert_instr(aes64ks1i))]
#[inline]
pub unsafe fn aes64ks1i(rs1: u64, rnum: u8) -> u64 {
macro_rules! aes64ks1i {
($imm_0_until_10:expr) => {{
let value: u64;
unsafe {
asm!(
concat!("aes64ks1i {rd},{rs1},", $imm_0_until_10),
rd = lateout(reg) value,
rs1 = in(reg) rs1,
options(pure, nomem, nostack),
)
}
value
}}
}
constify_imm_0_until_10!(rnum, aes64ks1i)
pub unsafe fn aes64ks1i<const RNUM: u8>(rs1: u64) -> u64 {
static_assert_imm_0_until_10!(RNUM);

_aes64ks1i(rs1 as i64, RNUM as i32) as u64
}

/// This instruction implements part of the KeySchedule operation for the AES Block cipher.
Expand Down
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