CI for MIPS/MIPS64

[gnzlbg]

To test the MIPS SIMD Architecture (MSA) intrinsics we need to setup CI for MIPS/MIP64 targets. This is a summary of the problems I've encountered so far.

• using MSA requires enabling floating-point features (fp64/fpxx). The current 32-bit MIPS targets ({mips,mipsel}-unknown-linux-gnu) do not have these enabled. Passing -C target-feature=+msa,+fp64 does not help:

  LLVM ERROR: MSA requires a 64-bit FPU register file (FR=1 mode). See -mattr=+fp64.
  

• enabling floating point probably will require a std library compiled with it enabled, this should help: bump mipsel isa leval and enable fpxx rust#48874

• qemu only supports two CPUs with MSA: p5600 (32-bit) and i6400 (64-bit).

• qemu has a bug in which the auxiliary vector bit for MSA is not set: https://bugs.launchpad.net/qemu/+bug/1754372 ; until that is fixed we can't really test run-time feature detection under qemu and must override it to test the intrinsics

• cross-compiling for i6400 is challenging. We need to set -C target-cpu=mips64r6 when compiling Rust. This is going to require the std lib to be compiled for this. Also, we need to set -march=mips64r6 when compiling C (e.g. for backtrace, auxv, etc.). The cross-compilation toolchains for this are not available in Ubuntu, only on Debian testing/unstable: libc6-dev-mips64r-cross. I haven't managed to get them to work (they seem buggy: missing headers, linking failurs, etc. they do not work out-of-the-box). One also must be careful of not cross-compiling against code that was compiled for mips64r2 since that will fail to link. All in all we might need to just use a different toolchain here, like the Codescape SDK. This explains how to set it up: https://github.com/v8mips/v8mips/wiki/Building-v8-for-MIPS

• cross-compiling for p5600 requires targeting -C target-cpu=mips64r5/-march=mips64r5. The toolchains for it look mature, they might even work out-of-the-box. We will probably still need to recompile the std library for these targets though.

I would be surprised if these were the only issues.

In my opinion, the most promising route towards CI for MS would be to focus on mips/mipsel and the p5600.

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cc @jcowgill @malbarbo @japaric

[gnzlbg]

QEMU 2.12 has auxv support for MIPS, which should enable us to run our tests there as well :)

[gnzlbg]

@rbirdic all mips build jobs currently have NORUN=1 in the .travis.yml, which means that these targets are only built, but the tests are not run on CI. AFAICT this is the only thing blocking the stabilization of the MIPS MSA intrinsics (that is, if this were to be fixed, we could open a mini-FCP to stabilize them).

[rbirdic]

@gnzlbg I am currently working on MIPS R6 build jobs that will run tests. We can't run tests for older versions of MIPS ISA, due to constraints imposed by QEMU.