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bump mipsel isa leval and enable fpxx #48874

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merged 3 commits into from
Mar 14, 2018
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jcowgill
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@jcowgill jcowgill commented Mar 9, 2018

This PR:

  • Bumps the default ISA level of the mipsel targets to mips32r2. The big endian mips targets are already built with mips32r2. This is the usual baseline for the MIPS ISA these days used by other projects, although it does drop support for the 4K processor (which was the only processor released with mips32 r1). Debian no longer supports pre-R2 processors. Using R2 also improves code generation in FPXX in certain circumstances.
  • Enables the FPXX floating point ABI[1] on 32-bit hard-float targets by default. This ABI adds some extra restrictions to the existing ABI which allows code to run on the two main floating point modes found on MIPS (FR0 and FR1) and remains compatible with the FR32 ABI currently in use. All code within an executable (including all shared libraries) must be compiled with FPXX/FP64 to be able to use MSA on 32-bit MIPS.
  • Enables the "nooddspreg" feature with FPXX. This feature is usually enabled whenever FPXX is. It also helps workaround some issues on Loongson processors. I'm hoping this will fix some test failures mentioned in 1.14.0 mipsel test failures: f32 #39013.
  • Adds the fp64 feature to the MIPS whitelist. This feature must be enabled to use MSA on 32-bit MIPS, otherwise LLVM will complain.

[1] See https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking

See this page for details about FPXX:
https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking

Using FPXX is the most compatible floating point mode available and
allows the generated code to work in both FR0 and FR1 modes of the
processor. Using MSA (MIPS SIMD) requires FR1, so to use any MSA code we
need a compatible floating point mode.

This commit also sets nooddspreg (disabling the use of odd numbered
single precision float registers) as recommended when enabling FPXX.
On 32-bit MIPS, enabling MSA requires also enabling the 64-bit FPU.
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Thanks for the pull request, and welcome! The Rust team is excited to review your changes, and you should hear from @michaelwoerister (or someone else) soon.

If any changes to this PR are deemed necessary, please add them as extra commits. This ensures that the reviewer can see what has changed since they last reviewed the code. Due to the way GitHub handles out-of-date commits, this should also make it reasonably obvious what issues have or haven't been addressed. Large or tricky changes may require several passes of review and changes.

Please see the contribution instructions for more information.

@rust-highfive rust-highfive added the S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. label Mar 9, 2018
@michaelwoerister
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r? @japaric

@sanxiyn
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sanxiyn commented Mar 14, 2018

@bors r+

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bors commented Mar 14, 2018

📌 Commit 0711a7a has been approved by sanxiyn

@bors bors added S-waiting-on-bors Status: Waiting on bors to run and complete tests. Bors will change the label on completion. and removed S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. labels Mar 14, 2018
kennytm added a commit to kennytm/rust that referenced this pull request Mar 14, 2018
bump mipsel isa leval and enable fpxx

This PR:
* Bumps the default ISA level of the mipsel targets to `mips32r2`. The big endian mips targets are already built with `mips32r2`. This is the usual baseline for the MIPS ISA these days used by other projects, although it does drop support for the 4K processor (which was the only processor released with mips32 r1). Debian no longer supports pre-R2 processors. Using R2 also improves code generation in FPXX in certain circumstances.
* Enables the FPXX floating point ABI[1] on 32-bit hard-float targets by default. This ABI adds some extra restrictions to the existing ABI which allows code to run on the two main floating point modes found on MIPS (FR0 and FR1) and remains compatible with the FR32 ABI currently in use. All code within an executable (including all shared libraries) must be compiled with FPXX/FP64 to be able to use MSA on 32-bit MIPS.
* Enables the "nooddspreg" feature with FPXX. This feature is usually enabled whenever FPXX is. It also helps workaround some issues on Loongson processors. I'm hoping this will fix some test failures mentioned in rust-lang#39013.
* Adds the `fp64` feature to the MIPS whitelist. This feature must be enabled to use MSA on 32-bit MIPS, otherwise LLVM will complain.

[1] See https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking
bors added a commit that referenced this pull request Mar 14, 2018
Rollup of 12 pull requests

- Successful merges: #48765, #48831, #48840, #48964, #48970, #48971, #48981, #48988, #48991, #48966, #48993, #48874
- Failed merges:
@bors bors merged commit 0711a7a into rust-lang:master Mar 14, 2018
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6 participants