Improve feature detect for combined aarch64 features

[adamgemmell]

LLVM's ssbs and mte target_features represent two Arm features. Linux's HWCAP also represents the same two features, so this is just a documentation update.

LLVM's ras target_feature represents two Arm features - FEAT_RAS and FEAT_RASv1p1. There is no runtime detection for this, so this is a no-op in stdarch.

LLVM's aes feature covers both FEAT_AES and FEAT_PMULL, but Linux exposes seperate feature bits. This patch makes the aes target_feature correctly shortcut runtime pmull detection and also makes the aes feature check for pmull at runtime to bring it in line with the target_feature behaviour. In practice I think this makes the two runtime features identical since the ID_AA64ISAR0_EL1 register does not allow for PMULL without AES. I haven't added a pmull target_feature because it would behave identically to the aes one, but I could do if you see fit.

#1432

For reference:
Linux HWCAPs are documented here: https://www.kernel.org/doc/html/latest/arch/arm64/elf_hwcaps.html
They reference the ID registers documented here: https://developer.arm.com/documentation/ddi0595/2021-12/AArch64-Registers
LLVM target features are defined here: https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AArch64/AArch64.td

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[adamgemmell]

I've bisected the CI failure down to the LLVM 18 upgrade - I'll be able to look into it next week if no-one gets there first.

[Amanieu]

LGTM once CI is fixed (when the nightly updates)