Add errors::PageFault

This covers the error code during a #PF.

Signed-off-by: Nathaniel McCallum <nathaniel@congru.us>

src/errors.rs

@@ -1,6 +1,7 @@
 //! This module contains errors and exception types.
 
 use bit_field::BitField;
+use bitflags::bitflags;
 
 /// Exception Error Codes
 ///
@@ -81,6 +82,42 @@ pub enum Exception {
     Security = 0x1E,
 }
 
+bitflags! {
+    /// The errors that can cause a page fault.
+    ///
+    /// This structure is defined by the following manual sections:
+    ///   * AMD Volume 2: 8.4.2
+    ///   * Intel Volume 3A: 4.7
+    pub struct PageFault: u32 {
+        /// The fault was caused permissions. Otherwise, missing entry.
+        const PERMISSIONS = 1 << 0;
+
+        /// The fault was caused by a write. Otherwise, a read.
+        const WRITE = 1 << 1;
+
+        /// The fault was user-mode. Otherwise, supervisor-mode.
+        const USER = 1 << 2;
+
+        /// The fault was caused by a reserved bit set.
+        const RESERVED = 1 << 3;
+
+        /// The fault was caused by an instruction fetch.
+        const INSTRUCTION = 1 << 4;
+
+        /// The fault was caused by protection key.
+        const PROTECTION_KEY = 1 << 5;
+
+        /// The fault was caused by shadow stack access (AMD-only).
+        const SHADOW_STACK = 1 << 6;
+
+        /// The fault was caused by SGX access-control requirements (Intel-only).
+        const SGX = 1 << 15;
+
+        /// The fault was caused by RMP violation (AMD-only).
+        const RMP = 1 << 31;
+    }
+}
+
 /// The index in a selector error
 #[derive(Copy, Clone, Debug, PartialEq, Eq)]
 pub enum SelectorIndex {