[LLVM][RVV 0.7.1] Use T-Head suggested naming schema (#30)

* [LLVM][RVV 0.7.1] `xtheadv` -> `xtheadvector`

* [LLVM][RVV 0.7.1] MC names (1/N)

* [LLVM][RVV 0.7.1] MC names (2/N)

* [LLVM][RVV 0.7.1] MC names (3/N)

* [LLVM][RVV 0.7.1] MC names (4/N)

* [LLVM][RVV 0.7.1] LLVM intrinsic names (5/N)

* [LLVM][RVV 0.7.1] LLVM intrinsic names (6/N)

* [LLVM][RVV 0.7.1] Pass all MC tests

* [LLVM][RVV 0.7.1] Pass all LLVM CodeGen tests

* [LLVM][RVV 0.7.1] `llvm.riscv.xv*` -> `llvm.riscv.th.v*`

* [Clang][RVV 0.7.1] `xv*` -> `th_v*`

* [Clang][RVV 0.7.1] Update tests

* [Clang][RVV 0.7.1] Update macros and headers with T-Head upstream

Ref: riscv-non-isa/rvv-intrinsic-doc#298

* [LLVM][RVV 0.7.1] Rename

* [Clang][RVV 0.7.1] Fix pragma

* [LLVM][RVV 0.7.1] Fix vleff tests

clang/include/clang/Basic/riscv_vector_xtheadv.td

@@ -99,7 +99,7 @@ void __riscv_vwrite_csr(enum RVV_CSR __csr, unsigned long __value) {
   }
 }
 }] in
-def xvread_xvwrite_csr: RVVHeader;
+def th_vread_th_vwrite_csr: RVVHeader;
 
 // vsetvl/vsetvlmax are a macro because they require constant integers in SEW
 // and LMUL.
@@ -108,55 +108,55 @@ let HeaderCode =
 
 /* These two builtins comes from the 1.0 implementation, */
 /* for compatibility, we forward these calls to the corresponding 0.7 builtins. */
-#define __builtin_rvv_vsetvli(avl, sew, lmul) __builtin_rvv_xvsetvl((size_t)(avl), sew, lmul)
-#define __builtin_rvv_vsetvlimax(sew, lmul)   __builtin_rvv_xvsetvlmax(sew, lmul)
+#define __builtin_rvv_vsetvli(avl, sew, lmul) __builtin_rvv_th_vsetvl((size_t)(avl), sew, lmul)
+#define __builtin_rvv_vsetvlimax(sew, lmul)   __builtin_rvv_th_vsetvlmax(sew, lmul)
 
-#define __riscv_vsetvl_e8m1(avl) __builtin_rvv_xvsetvl((size_t)(avl), 0, 0)
-#define __riscv_vsetvl_e8m2(avl) __builtin_rvv_xvsetvl((size_t)(avl), 0, 1)
-#define __riscv_vsetvl_e8m4(avl) __builtin_rvv_xvsetvl((size_t)(avl), 0, 2)
-#define __riscv_vsetvl_e8m8(avl) __builtin_rvv_xvsetvl((size_t)(avl), 0, 3)
+#define __riscv_vsetvl_e8m1(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 0, 0)
+#define __riscv_vsetvl_e8m2(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 0, 1)
+#define __riscv_vsetvl_e8m4(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 0, 2)
+#define __riscv_vsetvl_e8m8(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 0, 3)
 
-#define __riscv_vsetvl_e16m1(avl) __builtin_rvv_xvsetvl((size_t)(avl), 1, 0)
-#define __riscv_vsetvl_e16m2(avl) __builtin_rvv_xvsetvl((size_t)(avl), 1, 1)
-#define __riscv_vsetvl_e16m4(avl) __builtin_rvv_xvsetvl((size_t)(avl), 1, 2)
-#define __riscv_vsetvl_e16m8(avl) __builtin_rvv_xvsetvl((size_t)(avl), 1, 3)
+#define __riscv_vsetvl_e16m1(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 1, 0)
+#define __riscv_vsetvl_e16m2(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 1, 1)
+#define __riscv_vsetvl_e16m4(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 1, 2)
+#define __riscv_vsetvl_e16m8(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 1, 3)
 
-#define __riscv_vsetvl_e32m1(avl) __builtin_rvv_xvsetvl((size_t)(avl), 2, 0)
-#define __riscv_vsetvl_e32m2(avl) __builtin_rvv_xvsetvl((size_t)(avl), 2, 1)
-#define __riscv_vsetvl_e32m4(avl) __builtin_rvv_xvsetvl((size_t)(avl), 2, 2)
-#define __riscv_vsetvl_e32m8(avl) __builtin_rvv_xvsetvl((size_t)(avl), 2, 3)
+#define __riscv_vsetvl_e32m1(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 2, 0)
+#define __riscv_vsetvl_e32m2(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 2, 1)
+#define __riscv_vsetvl_e32m4(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 2, 2)
+#define __riscv_vsetvl_e32m8(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 2, 3)
 
 #if __riscv_v_elen >= 64
-#define __riscv_vsetvl_e64m1(avl) __builtin_rvv_xvsetvl((size_t)(avl), 3, 0)
-#define __riscv_vsetvl_e64m2(avl) __builtin_rvv_xvsetvl((size_t)(avl), 3, 1)
-#define __riscv_vsetvl_e64m4(avl) __builtin_rvv_xvsetvl((size_t)(avl), 3, 2)
-#define __riscv_vsetvl_e64m8(avl) __builtin_rvv_xvsetvl((size_t)(avl), 3, 3)
+#define __riscv_vsetvl_e64m1(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 3, 0)
+#define __riscv_vsetvl_e64m2(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 3, 1)
+#define __riscv_vsetvl_e64m4(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 3, 2)
+#define __riscv_vsetvl_e64m8(avl) __builtin_rvv_th_vsetvl((size_t)(avl), 3, 3)
 #endif
 
-#define __riscv_vsetvlmax_e8m1() __builtin_rvv_xvsetvlmax(0, 0)
-#define __riscv_vsetvlmax_e8m2() __builtin_rvv_xvsetvlmax(0, 1)
-#define __riscv_vsetvlmax_e8m4() __builtin_rvv_xvsetvlmax(0, 2)
-#define __riscv_vsetvlmax_e8m8() __builtin_rvv_xvsetvlmax(0, 3)
+#define __riscv_vsetvlmax_e8m1() __builtin_rvv_th_vsetvlmax(0, 0)
+#define __riscv_vsetvlmax_e8m2() __builtin_rvv_th_vsetvlmax(0, 1)
+#define __riscv_vsetvlmax_e8m4() __builtin_rvv_th_vsetvlmax(0, 2)
+#define __riscv_vsetvlmax_e8m8() __builtin_rvv_th_vsetvlmax(0, 3)
 
-#define __riscv_vsetvlmax_e16m1() __builtin_rvv_xvsetvlmax(1, 0)
-#define __riscv_vsetvlmax_e16m2() __builtin_rvv_xvsetvlmax(1, 1)
-#define __riscv_vsetvlmax_e16m4() __builtin_rvv_xvsetvlmax(1, 2)
-#define __riscv_vsetvlmax_e16m8() __builtin_rvv_xvsetvlmax(1, 3)
+#define __riscv_vsetvlmax_e16m1() __builtin_rvv_th_vsetvlmax(1, 0)
+#define __riscv_vsetvlmax_e16m2() __builtin_rvv_th_vsetvlmax(1, 1)
+#define __riscv_vsetvlmax_e16m4() __builtin_rvv_th_vsetvlmax(1, 2)
+#define __riscv_vsetvlmax_e16m8() __builtin_rvv_th_vsetvlmax(1, 3)
 
-#define __riscv_vsetvlmax_e32m1() __builtin_rvv_xvsetvlmax(2, 0)
-#define __riscv_vsetvlmax_e32m2() __builtin_rvv_xvsetvlmax(2, 1)
-#define __riscv_vsetvlmax_e32m4() __builtin_rvv_xvsetvlmax(2, 2)
-#define __riscv_vsetvlmax_e32m8() __builtin_rvv_xvsetvlmax(2, 3)
+#define __riscv_vsetvlmax_e32m1() __builtin_rvv_th_vsetvlmax(2, 0)
+#define __riscv_vsetvlmax_e32m2() __builtin_rvv_th_vsetvlmax(2, 1)
+#define __riscv_vsetvlmax_e32m4() __builtin_rvv_th_vsetvlmax(2, 2)
+#define __riscv_vsetvlmax_e32m8() __builtin_rvv_th_vsetvlmax(2, 3)
 
 #if __riscv_v_elen >= 64
-#define __riscv_vsetvlmax_e64m1() __builtin_rvv_xvsetvlmax(3, 0)
-#define __riscv_vsetvlmax_e64m2() __builtin_rvv_xvsetvlmax(3, 1)
-#define __riscv_vsetvlmax_e64m4() __builtin_rvv_xvsetvlmax(3, 2)
-#define __riscv_vsetvlmax_e64m8() __builtin_rvv_xvsetvlmax(3, 3)
+#define __riscv_vsetvlmax_e64m1() __builtin_rvv_th_vsetvlmax(3, 0)
+#define __riscv_vsetvlmax_e64m2() __builtin_rvv_th_vsetvlmax(3, 1)
+#define __riscv_vsetvlmax_e64m4() __builtin_rvv_th_vsetvlmax(3, 2)
+#define __riscv_vsetvlmax_e64m8() __builtin_rvv_th_vsetvlmax(3, 3)
 #endif
 
 }] in
-def xvsetvl_macro: RVVHeader;
+def th_vsetvl_macro: RVVHeader;
 
 let HasBuiltinAlias = false,
     HasVL = false,
@@ -165,14 +165,14 @@ let HasBuiltinAlias = false,
     Log2LMUL = [0],
     ManualCodegen = [{IntrinsicTypes = {ResultType};}] in // Set XLEN type
 {
-  def xvsetvl : RVVBuiltin<"", "zzKzKz", "i">;
-  def xvsetvlmax : RVVBuiltin<"", "zKzKz", "i">;
+  def th_vsetvl : RVVBuiltin<"", "zzKzKz", "i">;
+  def th_vsetvlmax : RVVBuiltin<"", "zKzKz", "i">;
 }
 
 //===----------------------------------------------------------------------===//
 // 12. Vector Integer Arithmetic Instructions
 //===----------------------------------------------------------------------===//
 
 let UnMaskedPolicyScheme = HasPassthruOperand in {
-  defm xvadd : RVVIntBinBuiltinSet;
+  defm th_vadd : RVVIntBinBuiltinSet;
 }

clang/lib/Basic/Targets/RISCV.cpp

@@ -200,12 +200,9 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
     Builder.defineMacro("__riscv_v_intrinsic", Twine(getVersionValue(0, 11)));
   }
 
-  if (ISAInfo->hasExtension("xtheadv")) {
-    // TODO: should we define __riscv_vector here?
-    Builder.defineMacro("__riscv_vector");
-    Builder.defineMacro("__riscv_vector_xtheadv");
-    // TODO: which intrinsic version? reuse the v0.11 for now.
-    Builder.defineMacro("__riscv_v_intrinsic", Twine(getVersionValue(0, 11)));
+  if (ISAInfo->hasExtension("xtheadvector")) {
+    // https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/298/files
+    Builder.defineMacro("__riscv_th_v_intrinsic", Twine(getVersionValue(0, 11)));
   }
 
   auto VScale = getVScaleRange(Opts);

clang/lib/Headers/CMakeLists.txt

@@ -385,12 +385,12 @@ if(ARM IN_LIST LLVM_TARGETS_TO_BUILD OR AArch64 IN_LIST LLVM_TARGETS_TO_BUILD)
     )
 endif()
 if(RISCV IN_LIST LLVM_TARGETS_TO_BUILD)
-  # Generate riscv_vector.h and riscv_vector_xtheadv.h
+  # Generate riscv_vector.h and riscv_th_vector.h
   clang_generate_header(-gen-riscv-vector-header riscv_vector.td riscv_vector.h)
-  clang_generate_header(-gen-riscv-xtheadv-header riscv_vector_xtheadv.td riscv_vector_xtheadv.h)
+  clang_generate_header(-gen-riscv-xtheadv-header riscv_vector_xtheadv.td riscv_th_vector.h)
   list(APPEND riscv_generated_files
     "${CMAKE_CURRENT_BINARY_DIR}/riscv_vector.h"
-    "${CMAKE_CURRENT_BINARY_DIR}/riscv_vector_xtheadv.h"
+    "${CMAKE_CURRENT_BINARY_DIR}/riscv_th_vector.h"
     )
 endif()
 

clang/lib/Parse/ParsePragma.cpp

@@ -4027,7 +4027,7 @@ void PragmaMaxTokensTotalHandler::HandlePragma(Preprocessor &PP,
 
 // Handle '#pragma clang riscv intrinsic vector'.
 //        '#pragma clang riscv intrinsic sifive_vector'
-//        '#pragma clang riscv intrinsic xtheadv_vector'.
+//        '#pragma clang riscv intrinsic thead_vector'.
 void PragmaRISCVHandler::HandlePragma(Preprocessor &PP,
                                       PragmaIntroducer Introducer,
                                       Token &FirstToken) {
@@ -4044,10 +4044,10 @@ void PragmaRISCVHandler::HandlePragma(Preprocessor &PP,
   PP.Lex(Tok);
   II = Tok.getIdentifierInfo();
   if (!II || !(II->isStr("vector") || II->isStr("sifive_vector") ||
-               II->isStr("xtheadv_vector"))) {
+               II->isStr("thead_vector"))) {
     PP.Diag(Tok.getLocation(), diag::warn_pragma_invalid_argument)
         << PP.getSpelling(Tok) << "riscv" << /*Expected=*/true
-        << "'vector', 'sifive_vector' or 'xtheadv_vector'";
+        << "'vector', 'sifive_vector' or 'thead_vector'";
     return;
   }
 
@@ -4062,6 +4062,6 @@ void PragmaRISCVHandler::HandlePragma(Preprocessor &PP,
     Actions.DeclareRISCVVBuiltins = true;
   else if (II->isStr("sifive_vector"))
     Actions.DeclareRISCVSiFiveVectorBuiltins = true;
-  else if (II->isStr("xtheadv_vector"))
+  else if (II->isStr("thead_vector"))
     Actions.DeclareRISCVXTHeadVBuiltins = true;
 }

clang/lib/Sema/SemaChecking.cpp

@@ -4608,10 +4608,10 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
   case RISCVVector::BI__builtin_rvv_vsetvlimax:
     return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
            CheckRISCVLMUL(TheCall, 1, true);
-  case RISCVVector::BI__builtin_rvv_xvsetvl:
+  case RISCVVector::BI__builtin_rvv_th_vsetvl:
     return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3) ||
            CheckRISCVLMUL(TheCall, 2, false);
-  case RISCVVector::BI__builtin_rvv_xvsetvlmax:
+  case RISCVVector::BI__builtin_rvv_th_vsetvlmax:
     return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) ||
            CheckRISCVLMUL(TheCall, 1, false);
   case RISCVVector::BI__builtin_rvv_vget_v: {
@@ -5419,20 +5419,20 @@ void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D) {
   if ((Ty->isRVVType(/* Bitwidth */ 64, /* IsFloat */ false) ||
        Ty->isRVVType(/* ElementCount */ 1)) &&
       (!TI.hasFeature("zve64x") &&
-       !TI.hasFeature("xtheadv")))
+       !TI.hasFeature("xtheadvector")))
     Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64x";
   if (Ty->isRVVType(/* Bitwidth */ 16, /* IsFloat */ true) &&
-      (!TI.hasFeature("zvfh") && !TI.hasFeature("xtheadv")))
+      (!TI.hasFeature("zvfh") && !TI.hasFeature("xtheadvector")))
     Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zvfh";
   if (Ty->isRVVType(/* Bitwidth */ 32, /* IsFloat */ true) &&
-      (!TI.hasFeature("zve32f") && !TI.hasFeature("xtheadv")))
+      (!TI.hasFeature("zve32f") && !TI.hasFeature("xtheadvector")))
     Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve32f";
   if (Ty->isRVVType(/* Bitwidth */ 64, /* IsFloat */ true) &&
-      (!TI.hasFeature("zve64d") && !TI.hasFeature("xtheadv")))
+      (!TI.hasFeature("zve64d") && !TI.hasFeature("xtheadvector")))
     Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d";
   // Given that caller already checked isRVVType() before calling this function,
   // if we don't have at least zve32x supported, then we need to emit error.
-  if (!TI.hasFeature("zve32x") && !TI.hasFeature("xtheadv"))
+  if (!TI.hasFeature("zve32x") && !TI.hasFeature("xtheadvector"))
     Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve32x";
 }
 

clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/rvv-error.c

@@ -1,16 +1,16 @@
-// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadv -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64V %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64V %s
 // RUN: not %clang_cc1 -triple riscv64 -emit-llvm-only %s 2>&1 | FileCheck %s --check-prefix=CHECK-RV64-ERR
 
 // CHECK-RV64V-LABEL: @test(
 // CHECK-RV64V-NEXT:  entry:
-// CHECK-RV64V-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.xvsetvl.i64(i64 1, i64 0, i64 0)
+// CHECK-RV64V-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.th.vsetvl.i64(i64 1, i64 0, i64 0)
 // CHECK-RV64V-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
 // CHECK-RV64V-NEXT:    ret i32 [[CONV]]
 //
 
-// CHECK-RV64-ERR: error: builtin requires at least one of the following extensions to be enabled: 'Xtheadv'
+// CHECK-RV64-ERR: error: builtin requires at least one of the following extensions to be enabled: 'Xtheadvector'
 
-#include <riscv_vector_xtheadv.h>
+#include <riscv_th_vector.h>
 
 int test() {
   return __builtin_rvv_vsetvli(1, 0, 0); // e8m1

clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/rvv-errors.c

@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 %s -triple=riscv64 -target-feature +xtheadv -fsyntax-only -verify
+// RUN: %clang_cc1 %s -triple=riscv64 -target-feature +xtheadvector -fsyntax-only -verify
 
 #include <riscv_vector.h>
 

clang/test/CodeGen/RISCV/rvv0p71-intrinsics-handcrafted/rvv-intrinsic-datatypes.cpp

@@ -1,9 +1,9 @@
-// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadv \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +xtheadvector \
 // RUN: -O0 -emit-llvm %s -o - | FileCheck %s
 
 #include <riscv_vector.h>
 
-// This test case tests the typedef generated under riscv_vector_xtheadv.h
+// This test case tests the typedef generated under riscv_th_vector.h
 
 // CHECK-LABEL: define dso_local void @_Z3foov
 // CHECK-SAME: () #[[ATTR0:[0-9]+]] {

clang/test/Driver/riscv-arch.c

@@ -416,9 +416,9 @@
 // RUN:   FileCheck -check-prefix=RV32-V-GOODVERS %s
 // RV32-V-GOODVERS: "-target-feature" "+v"
 
-// RUN: %clang --target=riscv32-unknown-elf -march=rv32i_xtheadv -### %s -c 2>&1 | \
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32i_xtheadvector -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-V0P7-GOODVERS %s
-// RV32-V0P7-GOODVERS: "-target-feature" "+xtheadv"
+// RV32-V0P7-GOODVERS: "-target-feature" "+xtheadvector"
 
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32iv1p0_zvl32b0p1 -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-ZVL-BADVERS %s

clang/test/Preprocessor/riscv-target-features.c

@@ -223,12 +223,13 @@
 // CHECK-V-EXT: __riscv_vector 1
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
-// RUN: -march=rv32i_xtheadv -x c -E -dM %s \
+// RUN: -march=rv32i_xtheadvector -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-V0P7-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu \
-// RUN: -march=rv64i_xtheadv -x c -E -dM %s \
+// RUN: -march=rv64i_xtheadvector -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-V0P7-EXT %s
-// CHECK-V0P7-EXT: __riscv_xtheadv 7000{{$}}
+// CHECK-V0P7-EXT: __riscv_th_v_intrinsic 11000{{$}}
+// CHECK-V0P7-EXT: __riscv_xtheadvector 7000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
 // RUN: -march=rv32izfhmin1p0 -x c -E -dM %s \

clang/test/Sema/riscv-bad-intrinsic-pragma.c

@@ -2,7 +2,7 @@
 // RUN:            2>&1 | FileCheck %s
 
 #pragma clang riscv intrinsic vvvv
-// CHECK:      warning: unexpected argument 'vvvv' to '#pragma riscv'; expected 'vector', 'sifive_vector' or 'xtheadv_vector' [-Wignored-pragmas]
+// CHECK:      warning: unexpected argument 'vvvv' to '#pragma riscv'; expected 'vector', 'sifive_vector' or 'thead_vector' [-Wignored-pragmas]
 
 #pragma clang riscv what + 3241
 // CHECK:      warning: unexpected argument 'what' to '#pragma riscv'; expected 'intrinsic' [-Wignored-pragmas]

clang/utils/TableGen/RISCVVEmitter.cpp

@@ -100,7 +100,7 @@ class RVVEmitter {
 public:
   RVVEmitter(RecordKeeper &R) : Records(R) {}
 
-  /// Emit riscv_vector.h or riscv_vector_xtheadv.h
+  /// Emit riscv_vector.h or riscv_th_vector.h
   void createHeader(raw_ostream &o, clang::RVVHeaderType Type);
 
   /// Emit all the __builtin prototypes and code needed by Sema.
@@ -328,11 +328,12 @@ void RVVEmitter::createHeader(raw_ostream &OS, clang::RVVHeaderType Type) {
         " */\n\n";
 
   if (Type == clang::RVVHeaderType::RVV) {
-    // `__riscv_vector_xtheadv` is defined in `RISCVTargetInfo::getTargetDefines`
-    // If in `riscv_vector.h` we found that the xtheadv extension is required and enabled,
-    // we forward the include directive to the real header containing intrinsics for xtheadv.
-    OS << "#ifdef __riscv_vector_xtheadv\n";
-    OS << "#include <riscv_vector_xtheadv.h>\n";
+    // `__riscv_th_v_intrinsic` is defined in `RISCVTargetInfo::getTargetDefines`
+    // If in `riscv_vector.h` we found that the xtheadvector extension is required and enabled,
+    // we forward the include directive to the desired one.
+    // https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/298/files
+    OS << "#if defined (__riscv_xtheadvector) && defined (__riscv_th_v_intrinsic)\n";
+    OS << "#include <riscv_th_vector.h>\n";
     OS << "#else\n\n";
     // Otherwise, we include the real header containing intrinsics for RVV 1.0
   }
@@ -348,10 +349,10 @@ void RVVEmitter::createHeader(raw_ostream &OS, clang::RVVHeaderType Type) {
     OS << "#ifndef __riscv_vector\n";
     break;
   case clang::RVVHeaderType::XTHEADV_VECTOR:
-    OS << "#ifndef __riscv_vector_xtheadv\n";
+    OS << "#ifndef __riscv_xtheadvector\n";
     break;
   }
-  OS << "#error \"Vector intrinsics require the vector extension.\"\n";
+  OS << "#error \"Vector intrinsics require either Vector extension or XTheadVector extension.\"\n";
   OS << "#endif\n\n";
 
   OS << "#ifdef __cplusplus\n";
@@ -363,7 +364,7 @@ void RVVEmitter::createHeader(raw_ostream &OS, clang::RVVHeaderType Type) {
     OS << "#pragma clang riscv intrinsic vector\n\n";
     break;
   case clang::RVVHeaderType::XTHEADV_VECTOR:
-    OS << "#pragma clang riscv intrinsic xtheadv_vector\n\n";
+    OS << "#pragma clang riscv intrinsic thead_vector\n\n";
     break;
   }
 
@@ -438,7 +439,7 @@ void RVVEmitter::createHeader(raw_ostream &OS, clang::RVVHeaderType Type) {
   OS << "#endif // __RISCV_VECTOR_H\n";
 
   if (Type == clang::RVVHeaderType::RVV) {
-    OS << "#endif // __riscv_vector_xtheadv\n\n";
+    OS << "#endif // __riscv_xtheadvector\n\n";
   }
 }
 
@@ -452,7 +453,7 @@ void RVVEmitter::createBuiltins(raw_ostream &OS, clang::RVVHeaderType Type) {
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
         "ATTRS, \""
-     << (Type == clang::RVVHeaderType::RVV ? "zve32x" : "xtheadv") << "\")\n";
+     << (Type == clang::RVVHeaderType::RVV ? "zve32x" : "xtheadvector") << "\")\n";
   OS << "#endif\n";
   for (auto &Def : Defs) {
     auto P =

clang/utils/TableGen/TableGenBackends.h

@@ -27,7 +27,7 @@ namespace clang {
 // Decide whether to emit header code
 // `#pragma clang riscv intrinsic vector` for RVV 1.0 (the `RVV`),
 // or
-// `#pragma clang riscv intrinsic xtheadv_vector` for RVV 0.7.1 (the
+// `#pragma clang riscv intrinsic thead_vector` for RVV 0.7.1 (the
 // `XTHEADV_VECTOR`).
 enum RVVHeaderType : uint8_t { RVV, XTHEADV_VECTOR };