[LLVM][XTHeadVector] Implement intrinsics for vand/vor/vxor. (#53)

* [LLVM][XTHeadVector] Define intrinsic functions for vand/vor/vxor.

* [LLVM][XTHeadVector] Define pseudos and then map intrinsics to them.

* [LLVM][XTHeadVector] Add test cases for vand/vor/vxor.

* [NFC][XTHeadVector] Update README.

README.md

@@ -35,6 +35,10 @@ Any feature not listed below but present in the specification should be consider
       - (Done) `vmadc.{vvm,vxm,vim}`
       - (Done) `vsbc.{vvm,vxm}`
       - (Done) `vmsbc.{vvm,vxm}`
+    - (Done) `12.4. Vector Bitwise Logical Instructions`
+      - (Done) `vand.{vv,vx,vi}`
+      - (Done) `vor.{vv,vx,vi}`
+      - (Done) `vxor.{vv,vx,vi}`
 - (WIP) Clang intrinsics related to the `XTHeadVector` extension:
   - (WIP) `6. Configuration-Setting and Utility`
     - (Done) `6.1. Set vl and vtype`

llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td

@@ -619,6 +619,11 @@ let TargetPrefix = "riscv" in {
   defm th_vmadc_carry_in : RISCVBinaryMaskOutWithV0;
   defm th_vsbc : RISCVBinaryWithV0;
   defm th_vmsbc_borrow_in : RISCVBinaryMaskOutWithV0;
+
+  // 12.4. Vector Single-Width Integer Add and Subtract
+  defm th_vand : XVBinaryAAX;
+  defm th_vor : XVBinaryAAX;
+  defm th_vxor : XVBinaryAAX;
 } // TargetPrefix = "riscv"
 
 let TargetPrefix = "riscv" in {

llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td

@@ -2192,6 +2192,21 @@ let Predicates = [HasVendorXTHeadV] in {
   defm : XVPatBinaryM_VM_XM<"int_riscv_th_vmsbc_borrow_in", "PseudoTH_VMSBC">;
 } // Predicates = [HasVendorXTHeadV]
 
+//===----------------------------------------------------------------------===//
+// 12.4. Vector Bitwise Logical Instructions
+//===----------------------------------------------------------------------===//
+let Predicates = [HasVendorXTHeadV] in {
+  defm PseudoTH_VAND : XVPseudoVALU_VV_VX_VI;
+  defm PseudoTH_VOR  : XVPseudoVALU_VV_VX_VI;
+  defm PseudoTH_VXOR : XVPseudoVALU_VV_VX_VI;
+}
+
+let Predicates = [HasVendorXTHeadV] in {
+  defm : XVPatBinaryV_VV_VX_VI<"int_riscv_th_vand", "PseudoTH_VAND", AllIntegerXVectors>;
+  defm : XVPatBinaryV_VV_VX_VI<"int_riscv_th_vor", "PseudoTH_VOR", AllIntegerXVectors>;
+  defm : XVPatBinaryV_VV_VX_VI<"int_riscv_th_vxor", "PseudoTH_VXOR", AllIntegerXVectors>;
+}
+
 //===----------------------------------------------------------------------===//
 // 12.14. Vector Integer Merge and Move Instructions
 //===----------------------------------------------------------------------===//