Update top.sv

src/top.sv

@@ -1,72 +1,3 @@
-//_\TLV_version 1d: tl-x.org, generated by SandPiper(TM) 1.14-2022/10/10-beta-Pro
-//_\source top.tlv 43
-//_\SV
-   // Include Tiny Tapeout Lab.
-   // Included URL: "https://raw.githubusercontent.com/os-fpga/Virtual-FPGA-Lab/af18805ea79802b83477cf86aff503e97ed7394a/tlv_lib/tiny_tapeout_lib.tlv"// Included URL: "https://raw.githubusercontent.com/os-fpga/Virtual-FPGA-Lab/a069f1e4e19adc829b53237b3e0b5d6763dc3194/tlv_lib/fpga_includes.tlv"
-//_\source top.tlv 756
-
-
-
-
-
-
-
-
-
-//_\SV
-   // Default Makerchip TL-Verilog Code Template
-
-
-
-// ================================================
-// A simple Makerchip Verilog test bench driving random stimulus.
-// Modify the module contents to your needs.
-// ================================================
-
-// Include the Makerchip module only in Makerchip. (Only because Yosys chokes on $urandom.)
-
-
-module top(input logic clk, input logic reset, input logic [31:0] cyc_cnt, output logic passed, output logic failed);
-   // Tiny tapeout I/O signals.
-   logic [7:0] ui_in, uo_out;
-
-   logic [31:0] r;
-   always @(posedge clk) r = 0;
-   assign ui_in = r[7:0];
-
-   logic ena = 1'b0;
-   logic rst_n = ! reset;
-
-
-//_\SV  // Reset line alignment.
-   /*
-   // Or, to provide specific inputs at specific times...
-   // BE SURE TO COMMENT THE ASSIGNMENT OF INPUTS ABOVE.
-   // BE SURE TO DRIVE THESE ON THE B-PHASE OF THE CLOCK (ODD STEPS).
-   // Driving on the rising clock edge creates a race with the clock that has unpredictable simulation behavior.
-   initial begin
-      #1  // Drive inputs on the B-phase (odd timesteps). 1 cycle == 2 timesteps.
-         ui_in = 8'h0;
-      #10 // Step past reset.
-         ui_in = 8'hFF;
-      // ...etc.
-   end
-   */
-
-   // Instantiate the Tiny Tapeout module.
-   tt_um_template tt(.*);
-
-   assign passed = uo_out[0];
-   assign failed = uo_out[1];
-endmodule
-
-
-
-// Provide a wrapper module to debounce input signals if requested.
-
-// The above macro expands to multiple lines. We enter a new \SV block to reset line tracking.
-//_\SV
-
 
 
 // =======================