riscv: telink: seperate ram for tl3218x .

- use retention mode to seperate ram.
- reserve more ram for ilm.

Signed-off-by: Haiwen Xia <haiwen.xia@telink-semi.com>

.github/workflows/chef.yaml

@@ -111,7 +111,7 @@ jobs:
                 platform: telink
             - name: Update Zephyr to specific revision (for developers purpose)
               shell: bash
-              run: scripts/run_in_build_env.sh "python3 scripts/tools/telink/update_zephyr.py c932a121fa785e02a57c80b80a494ad75f728a29"
+              run: scripts/run_in_build_env.sh "python3 scripts/tools/telink/update_zephyr.py 3186756b6338a3b1cad5b86037f3c5331ba8b4a8"
             - name: CI Examples Telink
               shell: bash
               run: |

.github/workflows/examples-telink.yaml

@@ -58,7 +58,7 @@ jobs:
                 gh-context: ${{ toJson(github) }}
 
             - name: Update Zephyr to specific revision (for developers purpose)
-              run: scripts/run_in_build_env.sh "python3 scripts/tools/telink/update_zephyr.py b6355f59ed78a1a735e9c4c97434ec95f4a27c0a"
+              run: scripts/run_in_build_env.sh "python3 scripts/tools/telink/update_zephyr.py 3186756b6338a3b1cad5b86037f3c5331ba8b4a8"
 
             - name: Build example Telink (B92 retention) Air Quality Sensor App
               # Run test for master and s07641069 PRs

config/telink/chip-module/Kconfig.defaults

@@ -218,15 +218,15 @@ config PWM
 
 endif
 
-if BOARD_TL7218X_RETENTION || BOARD_TL3218X_RETENTION
+if BOARD_TL7218X_RETENTION || BOARD_TL3218X_RETENTION || BOARD_TL3218X
 config SOC_SERIES_RISCV_TELINK_TLX_NON_RETENTION_RAM_CODE
     default n if PM
 
 config TELINK_TLX_MATTER_RETENTION_LAYOUT
-    default y if PM
+    default y if PM || BOARD_TL3218X
 
 config PWM
-    default n
+    default n if PM
 
 endif