riscv: telink: add some macro support for tl7218x .

- optimize retention power. Signed-off-by: Liang Zhong <liang.zhong@telink-semi.com>
s07641069 · Jan 21, 2025 · d6882ec · d6882ec
1 parent 3275e55
commit d6882ec
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Showing 2 changed files with 27 additions and 2 deletions.
diff --git a/config/telink/chip-module/Kconfig.defaults b/config/telink/chip-module/Kconfig.defaults
@@ -84,7 +84,7 @@ config HEAP_MEM_POOL_SIZE
 
 config COMMON_LIBC_MALLOC_ARENA_SIZE
     default 20716 if SOC_RISCV_TELINK_TL321X || SOC_SERIES_RISCV_TELINK_B9X_RETENTION
-    default 16384 if SOC_RISCV_TELINK_TL721X
+    default 20716 if SOC_RISCV_TELINK_TL721X
     default 12288
 
 config NET_IPV6_MLD
@@ -307,6 +307,19 @@ endchoice
 config CHIP_ENABLE_ICD_SUPPORT
 	default y if CHIP_THREAD_DEVICE_ROLE_SLEEPY_END_DEVICE
 
+config OPENTHREAD_CSMABACKOFF_OPTIMIZATION
+	bool "Skip the first backoff during sending data request"
+	depends on CHIP_ENABLE_ICD_SUPPORT
+	default y if SOC_SERIES_RISCV_TELINK_TLX_RETENTION || SOC_SERIES_RISCV_TELINK_B9X_RETENTION
+	default n
+
+config IEEE802154_TLX_OPTIMIZATION
+	bool "optimize the rf performance for tlx"
+	default y if SOC_SERIES_RISCV_TELINK_TLX_RETENTION
+	default n
+	help
+	  optimize the rf performance for tlx.
+
 config OPENTHREAD_THREAD_STACK_SIZE
     default 2400 if PM || SOC_RISCV_TELINK_TL321X
 

diff --git a/src/platform/OpenThread/GenericThreadStackManagerImpl_OpenThread.hpp b/src/platform/OpenThread/GenericThreadStackManagerImpl_OpenThread.hpp
@@ -66,6 +66,10 @@ extern "C" void otSysProcessDrivers(otInstance * aInstance);
 extern "C" void otAppCliInit(otInstance * aInstance);
 #endif
 
+#if defined CONFIG_IEEE802154_TLX_OPTIMIZATION && CONFIG_IEEE802154_TLX_OPTIMIZATION
+bool isThreadCommissioned = false;
+#endif /* CONFIG_IEEE802154_TLX_OPTIMIZATION */
+
 namespace chip {
 namespace DeviceLayer {
 namespace Internal {
@@ -372,6 +376,14 @@ bool GenericThreadStackManagerImpl_OpenThread<ImplClass>::_IsThreadAttached()
     curRole = otThreadGetDeviceRole(mOTInst);
     Impl()->UnlockThreadStack();
 
+#if defined CONFIG_IEEE802154_TLX_OPTIMIZATION && CONFIG_IEEE802154_TLX_OPTIMIZATION
+    if ((curRole != OT_DEVICE_ROLE_DISABLED && curRole != OT_DEVICE_ROLE_DETACHED))
+    {
+        if (isThreadCommissioned == false)
+            isThreadCommissioned = true;
+    }
+#endif /* CONFIG_IEEE802154_TLX_OPTIMIZATION */
+
     return (curRole != OT_DEVICE_ROLE_DISABLED && curRole != OT_DEVICE_ROLE_DETACHED);
 }
 
@@ -2111,4 +2123,4 @@ template class GenericThreadStackManagerImpl_OpenThread<ThreadStackManagerImpl>;
 } // namespace DeviceLayer
 } // namespace chip
 
-#endif // GENERIC_THREAD_STACK_MANAGER_IMPL_OPENTHREAD_IPP
+#endif // GENERIC_THREAD_STACK_MANAGER_IMPL_OPENTHREAD_IPP