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riscv:telink: disable retention ramcode proc.
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- will not proc ramcode in start.s .

Signed-off-by: Haiwen Xia <haiwen.xia@telink-semi.com>
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haiwentelink committed Dec 10, 2024
1 parent 5ac7add commit ec7f7e0
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Showing 3 changed files with 4 additions and 4 deletions.
2 changes: 1 addition & 1 deletion .github/workflows/chef.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -111,7 +111,7 @@ jobs:
platform: telink
- name: Update Zephyr to specific revision (for developers purpose)
shell: bash
run: scripts/run_in_build_env.sh "python3 scripts/tools/telink/update_zephyr.py 6992cc68609189a5eb9d7810416de8610dfccc51"
run: scripts/run_in_build_env.sh "python3 scripts/tools/telink/update_zephyr.py 5ac7adde5570ea2e22e19db1c2a7c43e34c43726"
- name: CI Examples Telink
shell: bash
run: |
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2 changes: 1 addition & 1 deletion .github/workflows/examples-telink.yaml
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Expand Up @@ -58,7 +58,7 @@ jobs:
gh-context: ${{ toJson(github) }}

- name: Update Zephyr to specific revision (for developers purpose)
run: scripts/run_in_build_env.sh "python3 scripts/tools/telink/update_zephyr.py 6992cc68609189a5eb9d7810416de8610dfccc51"
run: scripts/run_in_build_env.sh "python3 scripts/tools/telink/update_zephyr.py 5ac7adde5570ea2e22e19db1c2a7c43e34c43726"

- name: Build example Telink (B92 retention) Air Quality Sensor App
# Run test for master and s07641069 PRs
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4 changes: 2 additions & 2 deletions config/telink/chip-module/Kconfig.defaults
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Expand Up @@ -34,7 +34,7 @@ choice LOG_MODE
endchoice

choice MATTER_LOG_LEVEL_CHOICE
default MATTER_LOG_LEVEL_WRN if SOC_RISCV_TELINK_TL321X
default MATTER_LOG_LEVEL_DBG if SOC_RISCV_TELINK_TL321X
default MATTER_LOG_LEVEL_DBG
endchoice

Expand Down Expand Up @@ -223,7 +223,7 @@ endif
if BOARD_TL3218X_RETENTION

config SOC_SERIES_RISCV_TELINK_TLX_NON_RETENTION_RAM_CODE
default y if PM
default n if PM

config TELINK_TLX_MATTER_RETENTION_LAYOUT
default y if PM
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