This repository contains the code, schematics, and reports for Analysis of Sorting Algorithms. The project focuses on implementing and analyzing three sorting algorithms (Bubble Sort, Selection Sort, and Insertion Sort) in Verilog. The algorithms are synthesized using 180nm technology and evaluated for power consumption and timing performance.
The objective of this project is to implement Verilog code for sorting 8-bit unsigned numbers using three different algorithms: Bubble Sort, Selection Sort, and Insertion Sort. The implementation is then analyzed in terms of timing and power when synthesized in a 180nm process.
- Code: Contains the Verilog code for the three sorting algorithms:
Bubble Sort.vSelection Sort.vInsertion Sort.v
- Schematics: Includes the generated schematics for each algorithm.
- Reports: Contains the detailed reports, including power, area and timing analysis for each sorting algorithm.
- Simulations: Includes the simulation outputs for each sorting algorithm.
- Verilog: For implementing the sorting algorithms.
- NCLaunch: For simulating the Verilog code.
- Cadence Genus: For synthesizing the design and generating power and timing reports.
- 180nm Technology: For evaluating the synthesized design.
The results of the power and timing analysis for each algorithm are documented in the respective reports. A comparative analysis of the three algorithms is also provided in the project documentation.
This project successfully demonstrates the implementation and analysis of three different sorting algorithms using CMOS VLSI design techniques. The power and timing analysis provides insights into the efficiency of each algorithm when implemented in hardware.