Feb 22/24

This repository will be updated with competed tests for VHDL and the SystemVerilog version.
The repository will be come the home of the "Directed Test Bench System"

This should happen in the June-July time frame.

This repository currently houses what is considered to be a working test bench package.
The users document has been updated with the latest feature changes and addtions.
ttb_gen has been recoded, again,  so that it is able to use default packages on most Unix systems.
The repository now contains an initial self-test suite that tests the default instruction set.

GHDL scripts included.

Next will be some initial examples copied from the existing release
Some profiling tests will be added

Then some more complicated examples

Last step will be to re-write the test bench package to use  "line" type insteade of hard coded strings.  This is a large effort.