Skip to content

Commit

Permalink
Merge branch 'odroid-5.4.y' into sbc-5.4.y
Browse files Browse the repository at this point in the history
  • Loading branch information
@scpcom
scpcom committed Feb 6, 2021
2 parents c17e66d + 5477551 commit 005677b
Show file tree
Hide file tree
Showing 1,704 changed files with 675,369 additions and 4,194 deletions.
8 changes: 8 additions & 0 deletions Documentation/admin-guide/kernel-parameters.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2667,6 +2667,8 @@
mds=off [X86]
tsx_async_abort=off [X86]
kvm.nx_huge_pages=off [X86]
no_entry_flush [PPC]
no_uaccess_flush [PPC]

Exceptions:
This does not have any effect on
Expand Down Expand Up @@ -2989,6 +2991,8 @@

noefi Disable EFI runtime services support.

no_entry_flush [PPC] Don't flush the L1-D cache when entering the kernel.

noexec [IA-64]

noexec [X86]
Expand Down Expand Up @@ -3038,6 +3042,9 @@
nospec_store_bypass_disable
[HW] Disable all mitigations for the Speculative Store Bypass vulnerability

no_uaccess_flush
[PPC] Don't flush the L1-D cache after accessing user data.

noxsave [BUGS=X86] Disables x86 extended register state save
and restore using xsave. The kernel will fallback to
enabling legacy floating-point and sse state.
Expand Down Expand Up @@ -5144,6 +5151,7 @@
device);
j = NO_REPORT_LUNS (don't use report luns
command, uas only);
k = NO_SAME (do not use WRITE_SAME, uas only)
l = NOT_LOCKABLE (don't try to lock and
unlock ejectable media, not on uas);
m = MAX_SECTORS_64 (don't transfer more
Expand Down
2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/net/can/tcan4x5x.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@ tcan4x5x: tcan4x5x@0 {
spi-max-frequency = <10000000>;
bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
interrupt-parent = <&gpio1>;
interrupts = <14 GPIO_ACTIVE_LOW>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
device-state-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
device-wake-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
Expand Down
2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/net/nfc/nxp-nci.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ Example (for ARM-based BeagleBone with NPC100 NFC controller on I2C2):
clock-frequency = <100000>;

interrupt-parent = <&gpio1>;
interrupts = <29 GPIO_ACTIVE_HIGH>;
interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;

enable-gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
firmware-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
Expand Down
2 changes: 1 addition & 1 deletion Documentation/devicetree/bindings/net/nfc/pn544.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ Example (for ARM-based BeagleBone with PN544 on I2C2):
clock-frequency = <400000>;

interrupt-parent = <&gpio1>;
interrupts = <17 GPIO_ACTIVE_HIGH>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;

enable-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
firmware-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
Expand Down
4 changes: 2 additions & 2 deletions Documentation/networking/j1939.rst
View file
Original file line number Diff line number Diff line change
Expand Up @@ -414,8 +414,8 @@ Send:
.can_family = AF_CAN,
.can_addr.j1939 = {
.name = J1939_NO_NAME;
.pgn = 0x30,
.addr = 0x12300,
.addr = 0x30,
.pgn = 0x12300,
},
};
Expand Down
2 changes: 1 addition & 1 deletion Documentation/virt/kvm/mmu.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -420,7 +420,7 @@ If the generation number of the spte does not equal the global generation
number, it will ignore the cached MMIO information and handle the page
fault through the slow path.

Since only 19 bits are used to store generation-number on mmio spte, all
Since only 18 bits are used to store generation-number on mmio spte, all
pages are zapped when there is an overflow.

Unfortunately, a single memory access might access kvm_memslots(kvm) multiple
Expand Down
9 changes: 9 additions & 0 deletions Documentation/x86/topology.rst
View file
Original file line number Diff line number Diff line change
Expand Up @@ -41,6 +41,8 @@ Package
Packages contain a number of cores plus shared resources, e.g. DRAM
controller, shared caches etc.

Modern systems may also use the term 'Die' for package.

AMD nomenclature for package is 'Node'.

Package-related topology information in the kernel:
Expand All @@ -53,11 +55,18 @@ Package-related topology information in the kernel:

The number of dies in a package. This information is retrieved via CPUID.

- cpuinfo_x86.cpu_die_id:

The physical ID of the die. This information is retrieved via CPUID.

- cpuinfo_x86.phys_proc_id:

The physical ID of the package. This information is retrieved via CPUID
and deduced from the APIC IDs of the cores in the package.

Modern systems use this value for the socket. There may be multiple
packages within a socket. This value may differ from cpu_die_id.

- cpuinfo_x86.logical_proc_id:

The logical ID of the package. As we do not trust BIOSes to enumerate the
Expand Down
9 changes: 6 additions & 3 deletions Documentation/xtensa/mmu.rst
View file
Original file line number Diff line number Diff line change
Expand Up @@ -82,7 +82,8 @@ Default MMUv2-compatible layout::
+------------------+
| VMALLOC area | VMALLOC_START 0xc0000000 128MB - 64KB
+------------------+ VMALLOC_END
| Cache aliasing | TLBTEMP_BASE_1 0xc7ff0000 DCACHE_WAY_SIZE
+------------------+
| Cache aliasing | TLBTEMP_BASE_1 0xc8000000 DCACHE_WAY_SIZE
| remap area 1 |
+------------------+
| Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
Expand Down Expand Up @@ -124,7 +125,8 @@ Default MMUv2-compatible layout::
+------------------+
| VMALLOC area | VMALLOC_START 0xa0000000 128MB - 64KB
+------------------+ VMALLOC_END
| Cache aliasing | TLBTEMP_BASE_1 0xa7ff0000 DCACHE_WAY_SIZE
+------------------+
| Cache aliasing | TLBTEMP_BASE_1 0xa8000000 DCACHE_WAY_SIZE
| remap area 1 |
+------------------+
| Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
Expand Down Expand Up @@ -167,7 +169,8 @@ Default MMUv2-compatible layout::
+------------------+
| VMALLOC area | VMALLOC_START 0x90000000 128MB - 64KB
+------------------+ VMALLOC_END
| Cache aliasing | TLBTEMP_BASE_1 0x97ff0000 DCACHE_WAY_SIZE
+------------------+
| Cache aliasing | TLBTEMP_BASE_1 0x98000000 DCACHE_WAY_SIZE
| remap area 1 |
+------------------+
| Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
Expand Down
5 changes: 4 additions & 1 deletion Makefile
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 5
PATCHLEVEL = 4
SUBLEVEL = 77
SUBLEVEL = 87
EXTRAVERSION =
NAME = Kleptomaniac Octopus

Expand Down Expand Up @@ -802,8 +802,11 @@ DEBUG_CFLAGS += -gsplit-dwarf
else
DEBUG_CFLAGS += -g
endif
ifneq ($(LLVM_IAS),1)
KBUILD_AFLAGS += -Wa,-gdwarf-2
endif
endif

ifdef CONFIG_DEBUG_INFO_DWARF4
DEBUG_CFLAGS += -gdwarf-4
endif
Expand Down
16 changes: 16 additions & 0 deletions arch/Kconfig
View file
Original file line number Diff line number Diff line change
Expand Up @@ -131,6 +131,22 @@ config UPROBES
managed by the kernel and kept transparent to the probed
application. )

config HAVE_64BIT_ALIGNED_ACCESS
def_bool 64BIT && !HAVE_EFFICIENT_UNALIGNED_ACCESS
help
Some architectures require 64 bit accesses to be 64 bit
aligned, which also requires structs containing 64 bit values
to be 64 bit aligned too. This includes some 32 bit
architectures which can do 64 bit accesses, as well as 64 bit
architectures without unaligned access.

This symbol should be selected by an architecture if 64 bit
accesses are required to be 64 bit aligned in this way even
though it is not a 64 bit architecture.

See Documentation/unaligned-memory-access.txt for more
information on the topic of unaligned memory accesses.

config HAVE_EFFICIENT_UNALIGNED_ACCESS
bool
help
Expand Down
2 changes: 2 additions & 0 deletions arch/arc/include/asm/pgtable.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -135,8 +135,10 @@

#ifdef CONFIG_ARC_HAS_PAE40
#define PTE_BITS_NON_RWX_IN_PD1 (0xff00000000 | PAGE_MASK | _PAGE_CACHEABLE)
#define MAX_POSSIBLE_PHYSMEM_BITS 40
#else
#define PTE_BITS_NON_RWX_IN_PD1 (PAGE_MASK | _PAGE_CACHEABLE)
#define MAX_POSSIBLE_PHYSMEM_BITS 32
#endif

/**************************************************************************
Expand Down
23 changes: 15 additions & 8 deletions arch/arc/kernel/stacktrace.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -38,15 +38,15 @@

#ifdef CONFIG_ARC_DW2_UNWIND

static void seed_unwind_frame_info(struct task_struct *tsk,
struct pt_regs *regs,
struct unwind_frame_info *frame_info)
static int
seed_unwind_frame_info(struct task_struct *tsk, struct pt_regs *regs,
struct unwind_frame_info *frame_info)
{
/*
* synchronous unwinding (e.g. dump_stack)
* - uses current values of SP and friends
*/
if (tsk == NULL && regs == NULL) {
if (regs == NULL && (tsk == NULL || tsk == current)) {
unsigned long fp, sp, blink, ret;
frame_info->task = current;

Expand All @@ -65,11 +65,15 @@ static void seed_unwind_frame_info(struct task_struct *tsk,
frame_info->call_frame = 0;
} else if (regs == NULL) {
/*
* Asynchronous unwinding of sleeping task
* - Gets SP etc from task's pt_regs (saved bottom of kernel
* mode stack of task)
* Asynchronous unwinding of a likely sleeping task
* - first ensure it is actually sleeping
* - if so, it will be in __switch_to, kernel mode SP of task
* is safe-kept and BLINK at a well known location in there
*/

if (tsk->state == TASK_RUNNING)
return -1;

frame_info->task = tsk;

frame_info->regs.r27 = TSK_K_FP(tsk);
Expand Down Expand Up @@ -103,6 +107,8 @@ static void seed_unwind_frame_info(struct task_struct *tsk,
frame_info->regs.r63 = regs->ret;
frame_info->call_frame = 0;
}

return 0;
}

#endif
Expand All @@ -116,7 +122,8 @@ arc_unwind_core(struct task_struct *tsk, struct pt_regs *regs,
unsigned int address;
struct unwind_frame_info frame_info;

seed_unwind_frame_info(tsk, regs, &frame_info);
if (seed_unwind_frame_info(tsk, regs, &frame_info))
return 0;

while (1) {
address = UNW_PC(&frame_info);
Expand Down
5 changes: 0 additions & 5 deletions arch/arm/boot/dts/armada-xp-98dx3236.dtsi
View file
Original file line number Diff line number Diff line change
Expand Up @@ -266,11 +266,6 @@
reg = <0x11000 0x100>;
};

&i2c1 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11100 0x100>;
};

&mpic {
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
};
Expand Down
5 changes: 0 additions & 5 deletions arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
View file
Original file line number Diff line number Diff line change
Expand Up @@ -81,11 +81,6 @@
status = "okay";
};

&vuart {
// VUART Host Console
status = "okay";
};

&uart1 {
// Host Console
status = "okay";
Expand Down
4 changes: 2 additions & 2 deletions arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts
View file
Original file line number Diff line number Diff line change
Expand Up @@ -22,9 +22,9 @@
#size-cells = <1>;
ranges;

vga_memory: framebuffer@7f000000 {
vga_memory: framebuffer@9f000000 {
no-map;
reg = <0x7f000000 0x01000000>;
reg = <0x9f000000 0x01000000>; /* 16M */
};
};

Expand Down
7 changes: 7 additions & 0 deletions arch/arm/boot/dts/at91-sama5d3_xplained.dts
View file
Original file line number Diff line number Diff line change
Expand Up @@ -242,6 +242,11 @@
atmel,pins =
<AT91_PIOE 9 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PE9, conflicts with A9 */
};
pinctrl_usb_default: usb_default {
atmel,pins =
<AT91_PIOE 3 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
AT91_PIOE 4 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
};
};
Expand All @@ -259,6 +264,8 @@
&pioE 3 GPIO_ACTIVE_LOW
&pioE 4 GPIO_ACTIVE_LOW
>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_default>;
status = "okay";
};

Expand Down
7 changes: 7 additions & 0 deletions arch/arm/boot/dts/at91-sama5d4_xplained.dts
View file
Original file line number Diff line number Diff line change
Expand Up @@ -133,6 +133,11 @@
atmel,pins =
<AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
};
pinctrl_usb_default: usb_default {
atmel,pins =
<AT91_PIOE 11 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
AT91_PIOE 14 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
pinctrl_key_gpio: key_gpio_0 {
atmel,pins =
<AT91_PIOE 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
Expand All @@ -158,6 +163,8 @@
&pioE 11 GPIO_ACTIVE_HIGH
&pioE 14 GPIO_ACTIVE_HIGH
>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_default>;
status = "okay";
};

Expand Down
19 changes: 11 additions & 8 deletions arch/arm/boot/dts/at91sam9rl.dtsi
View file
Original file line number Diff line number Diff line change
Expand Up @@ -278,23 +278,26 @@
atmel,adc-use-res = "highres";

trigger0 {
trigger-name = "timer-counter-0";
trigger-name = "external-rising";
trigger-value = <0x1>;
trigger-external;
};

trigger1 {
trigger-name = "timer-counter-1";
trigger-value = <0x3>;
trigger-name = "external-falling";
trigger-value = <0x2>;
trigger-external;
};

trigger2 {
trigger-name = "timer-counter-2";
trigger-value = <0x5>;
trigger-name = "external-any";
trigger-value = <0x3>;
trigger-external;
};

trigger3 {
trigger-name = "external";
trigger-value = <0x13>;
trigger-external;
trigger-name = "continuous";
trigger-value = <0x6>;
};
};

Expand Down
4 changes: 2 additions & 2 deletions arch/arm/boot/dts/dra76x.dtsi
View file
Original file line number Diff line number Diff line change
Expand Up @@ -32,8 +32,8 @@
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&mcan_clk>, <&l3_iclk_div>;
clock-names = "cclk", "hclk";
clocks = <&l3_iclk_div>, <&mcan_clk>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
};
};
Expand Down
Loading

0 comments on commit 005677b

Please sign in to comment.