Add SystemVerilog syntax

[SeanMcLoughlin]

See #1580.

[sharkdp]

All other submodules have a https link. Not sure if that could cause any problems, but might make sense to change it even if only for the sake of consistency.

[g2p]

I think it should be changed away from SSH, yes.

[sharkdp]

Could you please explain shortly what Verilog and SystemVerilog are, why we need syntaxes for both, and why a SystemVerilog syntax would still be valuable if .v files are highlighted as Verilog, by default.

[SeanMcLoughlin]

Not sure if you mean to add the explanation in the comments of this file or here, but I'll add it here first:

Verilog is a hardware description language used to describe circuits at the register transfer level. It's used in the semiconductor, ASIC, and FPGA industries.

SystemVerilog is a superset of Verilog, which provides many more features, including object-oriented programming, a random constraint solver, an assertion language, functional coverage constructs, and several others.

Unless required to for tool reasons, most developers these days will be using SystemVerilog instead of Verilog. Most of the logic in your CPU/GPU is most likely programmed in SystemVerilog.

The reason I have .v for SystemVerilog and Verilog is because that's what the Sublime Text submodule I added has them defined as, and I didn't see a way to get around that without updating the submodule. Personally, I have never seen a SystemVerilog file defined with .v, and the Wikipedia article I linked above seems to agree. If you know of a way to avoid that without updating the submodule, I can add it to this PR to avoid this extension conflict.

[sharkdp]

The explanation was only for me, thank you! :-)

I somehow thought .v was commonly used by both languages, but if there is .sv for SystemVerilog, your solution here is completely fine.

[sharkdp]

Thank you for you contribution.