GitHub - shivam444/Single-Cycle-RISC-V-Processor: Implementation of a single cycle RISC-V processor in Verilog, for FPGA.

shivam444 / Single-Cycle-RISC-V-Processor Public

Implementation of a single cycle RISC-V processor in Verilog, for FPGA.

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Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
ALU.v		ALU.v
ALU_MOD.v		ALU_MOD.v
ALU_TB.sv		ALU_TB.sv
ALU_TB.v		ALU_TB.v
CONTROLLER.v		CONTROLLER.v
DATA_MEMORY.v		DATA_MEMORY.v
DATA_MEMORY_TB.sv		DATA_MEMORY_TB.sv
DATA_MEMORY_TB.v		DATA_MEMORY_TB.v
IMMEDIATE_GENERATOR.v		IMMEDIATE_GENERATOR.v
INSTRUCTION_MEMORY.v		INSTRUCTION_MEMORY.v
INSTRUCTION_MEMORY_TB.v		INSTRUCTION_MEMORY_TB.v
PROGRAM_COUNTER.v		PROGRAM_COUNTER.v
PROGRAM_COUNTER_TB.v		PROGRAM_COUNTER_TB.v
README.md		README.md
REGISTER_FILE.v		REGISTER_FILE.v
REGISTER_FILE_TB.v		REGISTER_FILE_TB.v
RISCV_PROCESSOR.v		RISCV_PROCESSOR.v
RISCV_PROCESSOR_TB.v		RISCV_PROCESSOR_TB.v
SEVEN_SEGMENT_DISPLAY.v		SEVEN_SEGMENT_DISPLAY.v
SINGLE_CYLE_RISC_V.v		SINGLE_CYLE_RISC_V.v
Single_Cycle_timing_report.txt		Single_Cycle_timing_report.txt
Single_Cycle_utilization_report.txt		Single_Cycle_utilization_report.txt
constraints.xdc		constraints.xdc
data_memory_in.coe		data_memory_in.coe
inst_mem_init.coe		inst_mem_init.coe
instruction_memory_init.coe		instruction_memory_init.coe
test_data.sv		test_data.sv