This project involves the design and implementation of a basic RISC-V processor core using Verilog. The core is based on the RV32I instruction set, which is a subset of the RISC-V ISA. The goal is to create a fully functional processor that can execute a range of instructions including arithmetic, logical, memory, and control operations.
- Arithmetic Logic Unit
- Control Unit
- Program Counter
- Data Memory
- Instruction Memory
- Register File
- SRAM with R/W/S features