RISC-V and Other Computer Architecture Projects

This project involves the design and implementation of a basic RISC-V processor core using Verilog. The core is based on the RV32I instruction set, which is a subset of the RISC-V ISA. The goal is to create a fully functional processor that can execute a range of instructions including arithmetic, logical, memory, and control operations.

Key Components

1. Arithmetic Logic Unit
2. Control Unit
3. Program Counter
4. Data Memory
5. Instruction Memory
6. Register File
7. SRAM with R/W/S features