add doc for assembly and visulization

docs/Docs/ToolChain/Vesyla-suite/v4/Assembly.md

@@ -0,0 +1,48 @@
+# Assembly of the Fabric
+
+The DRRA-2 is a template system. Each fabric instance is assembled from components in a library according to an architecture description.
+
+## DRRA Component Library
+
+The DRRA component library is currently hosted on github at [drra-component-lib](https://github.com/silagokth/drra-component-lib). In the *lib* folder, you can find the components for fabric, cells, controllers as well as resources.
+
+To set up the component library, you can clone the repository, compile it and set up the environment variable `VESYLA_SUITE_PATH_COMPONENTS` to point to the compiled library folder.
+
+```bash
+git clone git@github.com:silagokth/drra-component-lib.git
+cd drra-component-lib
+mkdir build
+cd build
+cmake ..
+make -j
+export VESYLA_SUITE_PATH_COMPONENTS=$(pwd)/library
+```
+
+## Fabric Assembly
+
+The fabric assembly is the process of generating the fabric instance from a user-defined architectural description file. The fabric instance is a collection of components from the component library. The assembly process will generate the fabric instance in the output directory.
+
+The assembly process consists of the following steps:
+
+1. Generate an elaborated architectural description file with expanded structural information.
+2. Generate the ISA description file by collecting all the supported instructions from each used component.
+3. Generate the RTL description file by collecting all the RTL descriptions from each used component.
+
+To assemble the fabric, you can use the following command:
+
+```bash
+vesyla-suite fabric assembly -a user_defined_arch.json -o output_dir
+```
+After the command is executed, the output directory will contain three folders: *arch*, *isa*, and *rtl*. The *arch* folder contains the elaborated architectural description file. The *isa* folder contains the ISA description file. The *rtl* folder contains the RTL description file.
+
+### Architecture Description Assembly
+
+The architecture description is a JSON file that describes the fabric instance. The user will define the input architectural description file according to the requirements of the application. Then the user will generate/elaborate the fabric instance and generate an elaborated architectural description file. This output file will be the basis of all the other assembly task of the fabric instance.
+
+### ISA Description Assembly
+
+The ISA description is a JSON file that describes the instruction set architecture of the fabric instance. The ISA description file is generated by collecting all the supported instructions from each used component in the fabric instance. This process will use the elaborated architectural description file as the input. Based on the used components, the ISA description of each component will be collected and merged into the final ISA description file.
+
+### RTL Description Assembly
+
+The RTL description consists of many system verilog files that describe the fabric instance. The RTL description file is generated by collecting all the RTL descriptions from each used component in the fabric instance. This process will use the elaborated architectural description file as the input.

docs/Docs/ToolChain/Vesyla-suite/v4/Extension.md

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+# DRRA Extension System
+
+## Important Concepts
+
+## Component Package Structure
+
+## Architecture Description
+
+## ISA Description
+
+## RTL Description
+
+## Timing Model
+
+## ISA-level Behavioral Model
+
+## CMake Compilation Setup

docs/Docs/ToolChain/Vesyla-suite/v4/Installation.md

@@ -1,19 +1,10 @@
 # Installation and Usage
 
-## Cheddar
+## AppImage
 
 !!! tip "Recommendation"
-    The easiest way to use vesyla-suite is to use the pre-installed version on Cheddar.
-
-Vesyla-suite is pre-installed on Cheddar. You can use it directly without any installation. Contact the system administrator if you need an account on Cheddar. Use the following command to check the version of vesyla-suite.
-
-```tcl
-vesyla-suite --version
-```
-
-## AppImage
 
-Vesyla-suite is also available as an AppImage. You can download the AppImage file from the <a href="https://kth-my.sharepoint.com/:u:/g/personal/yuyang2_ug_kth_se/EaQngYNaRslDlQsTL3-AkDIB64rXut2W5TtgFem5ULA5oA" target="_blank">here</a>. You should put the AppImage file in a directory in your PATH. For example, you can put the AppImage file in the */usr/bin* directory.
+Vesyla-suite is also available as an AppImage. You can download the AppImage file of a specific release from the [github page](https://github.com/silagokth/vesyla-suite-4/releases). You should put the AppImage file in a directory in your PATH. For example, you can put the AppImage file in the */usr/bin* directory.
 
 ```tcl
 sudo mv vesyla-suite /usr/bin/vesyla-suite

docs/Docs/ToolChain/Vesyla-suite/v4/InstructionSet.md

@@ -1,5 +1,218 @@
-# Instruction Set V4
 
-## v4.1 (Current)
 
---8<-- "Docs/ToolChain/Vesyla-suite/v4/InstructionSet/isa_4.1.md"
+# ISA Specification
+
+Instructions are 32-bit wide. The MSB indicates whether it's a control instruction or a resource instruction. [0]: control; [1]: resource; The next  bits represent the instruction opcode. The rest of the bits are used to encode the instruction content. For resource instructions, another  bits in the instruction content are used to indicate the slot number. The rest of the bits are used to encode the instruction content.
+
+Note that, specifically for resource instructions, if instruction opcode start with "11", the instruction contains a field that need to be replaced by RACCU registers if the filed is marked "dynamic".
+
+## ISA Format
+Parameter | Width | Description
+----------|-------|-------------------------
+instr_bitwidth | 32 | Instruction bitwidth
+instr_type_bitwidth | 1 | Instruction type bitwidth
+instr_opcode_bitwidth | 3 | Instruction opcode bitwidth
+instr_slot_bitwidth | 4 | Instruction slot bitwidth, only used for resource components
+
+## Instructions For Each Component
+
+### sequencer ( controller )
+
+
+
+#### halt [opcode=0]
+
+Field | Position | Width | Default Value | Description
+------|----------|-------|---------------|-------------------------
+
+#### wait [opcode=1]
+
+Field | Position | Width | Default Value | Description
+------|----------|-------|---------------|-------------------------
+mode | [28, 28] | 1 |0| Wait mode, 0 means wait for a number of cycles, 1 means wait for events.
+cycle | [27, 1] | 27 |0| If mode is 0, it means the extra cycles to wait excluding the current cycle when this wait instruction is issued. If the mode is 1, this is the 1-hot encoding of event slots.
+
+#### act [opcode=2]
+
+Field | Position | Width | Default Value | Description
+------|----------|-------|---------------|-------------------------
+ports | [28, 13] | 16 |0| 1-hot encoded slots that need to be activated.
+mode | [12, 9] | 4 |0| Filter mode: [0]: Continues ports start from slot X; [1] All port X in each slot; [2]: the predefined 64-bit activation code in internal activation memory location X.
+param | [8, 1] | 8 |0| The parameter for the filter mode.
+
+#### calc [opcode=3]
+
+Field | Position | Width | Default Value | Description
+------|----------|-------|---------------|-------------------------
+mode | [28, 23] | 6 |0| Calculation mode [0]:idle; [1]:add; [2]:sub; [3]:lls; [4]:lrs; [5]:mul; [6]:div; [7]:mod; [8]:bitand; [9]:bitor; [10]:bitinv; [11]:bitxor; [17]:eq; [18]:ne; [19]:gt; [20]:ge; [21]:lt; [22]:le; [32]:and; [33]:or; [34]:not;
+operand1 | [22, 19] | 4 |0| First operand.
+operand2_sd | [18, 18] | 1 |0| Is the second operand static or dynamic? [0]:s; [1]:d;
+operand2 | [17, 10] | 8 |0| Second operand.
+result | [9, 6] | 4 |0| The register to store the result. It could be the scalar register or flag register, depending on the calculation mode.
+
+#### brn [opcode=4]
+
+Field | Position | Width | Default Value | Description
+------|----------|-------|---------------|-------------------------
+reg | [28, 25] | 4 |0| The flag register
+target_true | [24, 16] | 9 |0| The PC to jump to in case the condition is true. The PC is relative to the current PC.
+target_false | [15, 7] | 9 |0| The PC to jump to in case the condition is false. The PC is relative to the current PC.
+
+### swb ( resource )
+
+
+
+#### swb [opcode=4]
+
+Field | Position | Width | Default Value | Description
+------|----------|-------|---------------|-------------------------
+option | [24, 23] | 2 |0| configuration option
+channel | [22, 19] | 4 |0| Bus channel. Note: if the SWB is implemented by a crossbar, the channel is always equals to the target slot.
+source | [18, 15] | 4 |0| Source slot.
+target | [14, 11] | 4 |0| Target slot.
+
+#### route [opcode=5]
+
+Field | Position | Width | Default Value | Description
+------|----------|-------|---------------|-------------------------
+option | [24, 23] | 2 |0| configuration option
+sr | [22, 22] | 1 |0| Send or receive. [0]:s; [1]:r;
+source | [21, 18] | 4 |0| 1-hot encoded direction: E/N/W/S. If it's a receive instruction, the direction can only have 1 bit set to 1.
+target | [17, 2] | 16 |0| 1-hot encoded slot number. If it's a send instruction, the slot can only have 1 bit set to 1.
+
+### iosram_top ( resource )
+
+
+
+#### dsu [opcode=6]
+
+Field | Position | Width | Default Value | Description
+------|----------|-------|---------------|-------------------------
+init_addr_sd | [24, 24] | 1 |0| Is initial address static or dynamic? [0]:s; [1]:d;
+init_addr | [23, 8] | 16 |0| Initial address
+port | [7, 6] | 2 |0| The port number [0]:read narrow; [1]:read wide; [2]:write narrow; [3]:write wide;
+
+#### rep [opcode=0]
+
+Field | Position | Width | Default Value | Description
+------|----------|-------|---------------|-------------------------
+port | [24, 23] | 2 |0| The port number [0]:read narrow; [1]:read wide; [2]:write narrow; [3]:write wide;
+level | [22, 19] | 4 |0| The level of the REP instruction. [0]: inner most level, [15]: outer most level.
+iter | [18, 13] | 6 |0| level-1 iteration - 1.
+step | [12, 7] | 6 |1| level-1 step
+delay | [6, 1] | 6 |0| delay
+
+#### repx [opcode=1]
+
+Field | Position | Width | Default Value | Description
+------|----------|-------|---------------|-------------------------
+port | [24, 23] | 2 |0| The port number [0]:read narrow; [1]:read wide; [2]:write narrow; [3]:write wide;
+level | [22, 19] | 4 |0| The level of the REP instruction. [0]: inner most level, [15]: outer most level.
+iter | [18, 13] | 6 |0| level-1 iteration - 1.
+step | [12, 7] | 6 |1| level-1 step
+delay | [6, 1] | 6 |0| delay
+
+### rf ( resource )
+
+
+
+#### dsu [opcode=6]
+
+Field | Position | Width | Default Value | Description
+------|----------|-------|---------------|-------------------------
+init_addr_sd | [24, 24] | 1 |0| Is initial address static or dynamic? [0]:s; [1]:d;
+init_addr | [23, 8] | 16 |0| Initial address
+port | [7, 6] | 2 |0| The port number [0]:read narrow; [1]:read wide; [2]:write narrow; [3]:write wide;
+
+#### rep [opcode=0]
+
+Field | Position | Width | Default Value | Description
+------|----------|-------|---------------|-------------------------
+port | [24, 23] | 2 |0| The port number [0]:read narrow; [1]:read wide; [2]:write narrow; [3]:write wide;
+level | [22, 19] | 4 |0| The level of the REP instruction. [0]: inner most level, [15]: outer most level.
+iter | [18, 13] | 6 |0| level-1 iteration - 1.
+step | [12, 7] | 6 |1| level-1 step
+delay | [6, 1] | 6 |0| delay
+
+#### repx [opcode=1]
+
+Field | Position | Width | Default Value | Description
+------|----------|-------|---------------|-------------------------
+port | [24, 23] | 2 |0| The port number [0]:read narrow; [1]:read wide; [2]:write narrow; [3]:write wide;
+level | [22, 19] | 4 |0| The level of the REP instruction. [0]: inner most level, [15]: outer most level.
+iter | [18, 13] | 6 |0| level-1 iteration - 1.
+step | [12, 7] | 6 |1| level-1 step
+delay | [6, 1] | 6 |0| delay
+
+### dpu ( resource )
+
+
+
+#### dpu [opcode=3]
+
+Field | Position | Width | Default Value | Description
+------|----------|-------|---------------|-------------------------
+option | [24, 23] | 2 |0| Configuration option.
+mode | [22, 18] | 5 |0| The DPU mode.  [0]:idle; [1]:add; [2]:sum_acc; [3]:add_const; [4]:subt; [5]:subt_abs; [6]:mode_6; [7]:mult; [8]:mult_add; [9]:mult_const; [10]:mac; [11]:ld_ir; [12]:axpy; [13]:max_min_acc; [14]:max_min_const; [15]:mode_15; [16]:max_min; [17]:shift_l; [18]:shift_r; [19]:sigm; [20]:tanhyp; [21]:expon; [22]:lk_relu; [23]:relu; [24]:div; [25]:acc_softmax; [26]:div_softmax; [27]:ld_acc; [28]:scale_dw; [29]:scale_up; [30]:mac_inter; [31]:mode_31;
+immediate | [17, 2] | 16 |0| The immediate field used by some DPU modes.
+
+#### rep [opcode=0]
+
+Field | Position | Width | Default Value | Description
+------|----------|-------|---------------|-------------------------
+port | [24, 23] | 2 |0| The port number [0]:read narrow; [1]:read wide; [2]:write narrow; [3]:write wide;
+level | [22, 19] | 4 |0| The level of the REP instruction. [0]: inner most level, [15]: outer most level.
+iter | [18, 13] | 6 |0| level-1 iteration - 1.
+step | [12, 7] | 6 |1| level-1 step
+delay | [6, 1] | 6 |0| delay
+
+#### repx [opcode=1]
+
+Field | Position | Width | Default Value | Description
+------|----------|-------|---------------|-------------------------
+port | [24, 23] | 2 |0| The port number [0]:read narrow; [1]:read wide; [2]:write narrow; [3]:write wide;
+level | [22, 19] | 4 |0| The level of the REP instruction. [0]: inner most level, [15]: outer most level.
+iter | [18, 13] | 6 |0| level-1 iteration - 1.
+step | [12, 7] | 6 |1| level-1 step
+delay | [6, 1] | 6 |0| delay
+
+#### fsm [opcode=2]
+
+Field | Position | Width | Default Value | Description
+------|----------|-------|---------------|-------------------------
+port | [24, 23] | 2 |0| The port number
+delay_0 | [22, 16] | 7 |0| Delay between state 0 and 1.
+delay_1 | [15, 9] | 7 |0| Delay between state 1 and 2.
+delay_2 | [8, 2] | 7 |0| Delay between state 2 and 3.
+
+### iosram_btm ( resource )
+
+
+
+#### dsu [opcode=6]
+
+Field | Position | Width | Default Value | Description
+------|----------|-------|---------------|-------------------------
+init_addr_sd | [24, 24] | 1 |0| Is initial address static or dynamic? [0]:s; [1]:d;
+init_addr | [23, 8] | 16 |0| Initial address
+port | [7, 6] | 2 |0| The port number [0]:read narrow; [1]:read wide; [2]:write narrow; [3]:write wide;
+
+#### rep [opcode=0]
+
+Field | Position | Width | Default Value | Description
+------|----------|-------|---------------|-------------------------
+port | [24, 23] | 2 |0| The port number [0]:read narrow; [1]:read wide; [2]:write narrow; [3]:write wide;
+level | [22, 19] | 4 |0| The level of the REP instruction. [0]: inner most level, [15]: outer most level.
+iter | [18, 13] | 6 |0| level-1 iteration - 1.
+step | [12, 7] | 6 |1| level-1 step
+delay | [6, 1] | 6 |0| delay
+
+#### repx [opcode=1]
+
+Field | Position | Width | Default Value | Description
+------|----------|-------|---------------|-------------------------
+port | [24, 23] | 2 |0| The port number [0]:read narrow; [1]:read wide; [2]:write narrow; [3]:write wide;
+level | [22, 19] | 4 |0| The level of the REP instruction. [0]: inner most level, [15]: outer most level.
+iter | [18, 13] | 6 |0| level-1 iteration - 1.
+step | [12, 7] | 6 |1| level-1 step
+delay | [6, 1] | 6 |0| delay

docs/Docs/ToolChain/Vesyla-suite/v4/InstructionSet.md.bk

@@ -0,0 +1,5 @@
+# Instruction Set V4
+
+## v4.1 (Current)
+
+--8<-- "Docs/ToolChain/Vesyla-suite/v4/InstructionSet/isa_4.1.md"

docs/Docs/ToolChain/Vesyla-suite/v4/Visualization.md

@@ -0,0 +1,13 @@
+# Visualization of DRRA Fabric
+
+The visualization of the DRRA fabric is generated by the `archvis` command of the Vesyla-suite. The visualization is generated in the form of a PDF file and an SVG file.
+
+## Command
+
+Assuming you want to generate the visualization of the DRRA fabric to the current directory according to the architectural description file `arch.json`, you can use the following command:
+
+```bash
+$ vesyla-suite archvis -a arch.json -o .
+```
+
+After the command is executed, you will find one PDF file and one SVG file are generated in the current directory. Both contains the same visualization of the DRRA fabric.

mkdocs.yml

@@ -48,27 +48,11 @@ nav:
                   - Docs/ToolChain/Vesyla-suite/v4/InstructionSet.md
                   - Docs/ToolChain/Vesyla-suite/v4/Tutorial_DRRA.md
                   - Docs/ToolChain/Vesyla-suite/v4/ProgrammingGuide.md
+                  - Docs/ToolChain/Vesyla-suite/v4/Assembly.md
+                  - Docs/ToolChain/Vesyla-suite/v4/Visualization.md
+                  - Docs/ToolChain/Vesyla-suite/v4/Extension.md
                   - Docs/ToolChain/Vesyla-suite/v4/IO.md
                   - Docs/ToolChain/Vesyla-suite/v4/Scheduling.md
-
-  #       - Sylva:
-  #         - Docs/ToolChain/Sylva/Overview.md
-  #     - Library:
-  #       - Docs/Library/Overview.md
-  #       - BLAS:
-  #         - Docs/Library/BLAS/Overview.md
-  #         - L3:
-  #           - Docs/Library/BLAS/L3/gemm.md
-  #       - NN:
-  #         - Docs/Library/NN/Overview.md
-  #       - Interleaver:
-  #         - Docs/Library/Interleaver/Overview.md
-  #       - FFT:
-  #         - Docs/Library/FFT/Overview.md
-  #     - Appliction:
-  #       - Docs/Application/Overview.md
-  #       - SiLagoDSP:
-  #         - Docs/Application/SiLagoDSP/Fast-Fourier-Projection.md
   - About:
       - About/About.md
       - About/License.md