The Advanced VLSI Laboratory is a Center of Excellence (CoE) for training and R&D work in the area of CMOS integrated circuits (IC) and electronic system design & manufacturing (ESDM). The CoE's primary goal is to provide an ecosystem for fostering real-life, project-based learning for the next generation engineering students and fresh graduates aspiring to start a career in VLSI industry. This will allow our students to be industry ready, bridging a critical gap between the academia and industry.
- Training undergraduates and fresh hires to make them industry-ready in various VLSI domains including CMOS design and layout, PDK development, DRAM verification, standard-cell development.
- Execute turn-key projects using industry-standard integrated circuit technologies. This includes system design, circuit design, simulation and layout of mixed-signal IP blocks. Assembly of chip-level layout and full industrial-grade temperature (-40C to 125C) characterization.
- Capable of design, layout and characterize industry-grade analog and digital IP blocks including but not limited to bandgap reference, analog-to-digital converters, digital-to-analog converters, Serial Protocol Interface (SPI), I2C, oscillators, Phase-Locked Loops (PLLs), SRAM, Linear regulators and switch-capacitor power management ICs.
- NDA with leading semiconductor foundries including XFAB, TSMC, UMC with access ranging from 1um CMOS 600V process to 28nm LV CMOS process.
The primary goal is to collaborate with the industry and through various R&D and training activities, make our students industry-ready. We collaborate with various industry partners for R&D, training and fabrication activities. Our partners include:
- STMicroelectronics, Noida, India
- Micron Technology, Hyderabad, India
- Boston Microtechnology, Greater Boston, USA
- Sevya Multimedia, Noida, India
- XFAB, Erfurt, Germany
- Innatera Nanosystems B.V., Delft, The Netherlands
- Muse Semiconductor, Colorado, USA
- VLSI Experts, Noida, India
- Faculties with wide ranging experience in industry and academia to teach, train and execute industry projects. See Faculty Profiles Here
- Collaboration with industry experts to fill expertise gaps in training and project execution.
- Enterprise-grade Electronic Design Automation (EDA) tools from Cadence Design Systems and Siemens EDA (Previously Mentor Graphics).
- Collaboration with world-class foundries such as XFAB and TSMC to fabricate our designed integrated circuits.
- Enterprise-grade IT infrastructure:
- 2 Enterprise NAS server hosting all project, technology and EDA files.
- 40-Core Compute server for high-performance R&D work.
- 30-workstation Advanced VLSI Lab for research, training and hands-on workshops.
- 12-seater Training Lab equiped with 12 workstation and conferencing system for industry projects and trainings.
- All workstations and servers connected across the campus through a fiber network backbone.
- All workstations and servers running CentOS linux OS are manged centrally.
- Full equipped test laboratory to conduct training and consulting for integrated circuit characterization.
- A 8-seater office space for executing industry projects.
- Design, layout, fabricate and characterization of an integrated circuit (IC) with SPI-accessible SRAM, I2C-accessible characterization registers and an innovative compact bandgap reference in 0.6um CMOS technology.
- Design, layout, and characterization of various analog IP blocks including bandgap reference, temperature-controlled current source, ring oscillator in 0.18um 200V CMOS technology. This was part of an industry collaboration project which has been fabricated and characterized.
- Design and layout of various analog IP blocks (bandgap reference, power management, current-steering DAC) in 28nm CMOS technology. This was part of an industry collaboration project that has been fabricated and currently being characterized.
- Undergraduate training in CMOS VLSI design and layout.
- Training new hires for industry project in various VLSI domains including simulation, layout, PDK design and DRAM verification.