Changed speedgrade to -3

sinara-hw · Feb 16, 2021 · 63c775d · 63c775d
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diff --git a/PCB-Layout/Kasli-SOC.PCBDOC b/PCB-Layout/Kasli-SOC.PCBDOC
diff --git a/Schematics/Kasli-SOC_bank0.SchDoc b/Schematics/Kasli-SOC_bank0.SchDoc
diff --git a/Schematics/Kasli-SOC_bank112.SchDoc b/Schematics/Kasli-SOC_bank112.SchDoc
diff --git a/Schematics/Kasli-SOC_bank12.SchDoc b/Schematics/Kasli-SOC_bank12.SchDoc
diff --git a/Schematics/Kasli-SOC_bank13.SchDoc b/Schematics/Kasli-SOC_bank13.SchDoc
diff --git a/Schematics/Kasli-SOC_bank33-34-35.SchDoc b/Schematics/Kasli-SOC_bank33-34-35.SchDoc
diff --git a/Schematics/Kasli-SOC_bank500-501.SchDoc b/Schematics/Kasli-SOC_bank500-501.SchDoc
diff --git a/Schematics/Kasli-SOC_bank502_DDR.SchDoc b/Schematics/Kasli-SOC_bank502_DDR.SchDoc